summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-08-01arch/x86: Enable postcar consoleLee Leahy
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie
2016-06-28riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handlerJonathan Neuschäfer
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
2016-06-28arch/riscv: Move _start to the beginning of the bootblockJonathan Neuschäfer
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
2016-06-24arch/x86/smbios: Correct manufacturer IDElyes HAOUAS
2016-06-22ACPI S3: Add common recovery codeKyösti Mälkki
2016-06-22ACPI S3: Fix prohibited wakeupKyösti Mälkki
2016-06-22ACPI S3: Split support for HAVE_ACPI_RESUMEKyösti Mälkki
2016-06-22ACPI S3: Move SMP trampoline recoveryKyösti Mälkki
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
2016-06-20ACPI S3: Cleanup RSDP referenceKyösti Mälkki
2016-06-20arch/x86/smbios: Add DRAM manufacturerPatrick Rudolph
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
2016-06-12arch/riscv: Compile with -mcmodel=medanyJonathan Neuschäfer
2016-06-12arch/riscv: Add misc.c to bootblock/romstage to get udelay()Jonathan Neuschäfer
2016-06-12arch/riscv: copy read/write8/16/32 from x86Jonathan Neuschäfer
2016-06-12arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constantJonathan Neuschäfer
2016-06-11arch/x86: Support "weak" BIST and timestamp save routinesLee Leahy
2016-06-11arch/x86: Add debug spinloops in assembly_entry.SLee Leahy
2016-06-11arch/x86: Add debug spinloopLee Leahy
2016-06-09mainboard: Support ROM_SIZE > 16 MiBLee Leahy
2016-06-09arch/x86: Enable SSE in bootblock_crt0.SLee Leahy
2016-06-02SMBIOS: Implement SKU fieldKyösti Mälkki
2016-05-28acpi_device: Add support for writing ACPI Device PropertiesDuncan Laurie
2016-05-28acpi_device: Add support for writing ACPI SPI descriptorsDuncan Laurie
2016-05-28acpi_device: Add support for writing ACPI I2C descriptorsDuncan Laurie
2016-05-28acpi_device: Add support for writing ACPI GPIO descriptorsDuncan Laurie
2016-05-28acpi_device: Add support for writing ACPI Interrupt descriptorsDuncan Laurie
2016-05-27arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCKAaron Durbin
2016-05-24arm64: Add stack dump to exception handlerJulius Werner
2016-05-21device: Add an ACPI device name and path concept to devicesDuncan Laurie
2016-05-21acpigen: Add function to generate ToUUID() from a stringDuncan Laurie
2016-05-19arch/x86: Include timestamp.c in all stagesAlexandru Gagniuc
2016-05-17acpigen: Fix ?: operator confusionJonathan Neuschäfer
2016-05-16acpigen: Add functions to generate _STA() and _PRW()Duncan Laurie
2016-05-16acpigen: Add an abstracted integer output methodDuncan Laurie
2016-05-16acpigen: Add helper functions for stringsDuncan Laurie
2016-05-16acpigen: Add helpers for word/dword outputDuncan Laurie
2016-05-10arch/arm64: add FRAMEBUFFER region macros to memlayoutLin Huang
2016-05-09smbios: Add SuperTalent SPD IDTimothy Pearson
2016-05-09arch/armv7: Fix end index calculation in mmu_config_range_kbVaradarajan Narayanan
2016-05-03arch/x86: Drop CBFS_BASE_ADDRESSPatrick Georgi
2016-05-03build system: remove CBFSTOOL_PRE1_OPTSPatrick Georgi
2016-05-02arch/x86/assembly_entry: allow early post CAR stages to use common codeAaron Durbin
2016-05-02arch/x86/asembly_entry: reorder conditional stage entry macrosAaron Durbin
2016-05-02lib/coreboot_table: use the architecture dependent table sizeAaron Durbin
2016-05-02arch: introduce architecture dependent common variablesAaron Durbin
2016-05-02x86/memlayout.h: Do not include data/bss sections in C_ENVIRONMENT_BOOTBLOCKFurquan Shaikh
2016-04-21lib: add common write_tables() implementationAaron Durbin
2016-04-21lib/coreboot_table: add architecture hooks for adding tablesAaron Durbin
2016-04-21lib/bootmem: allow architecture specific bootmem rangesAaron Durbin
2016-04-21arch/x86: remove low coreboot table supportAaron Durbin
2016-04-21arch/x86: clean up write_tables()Aaron Durbin
2016-04-21arch: only print cbmem entries in one placeAaron Durbin
2016-04-21arch: use Kconfig variable for coreboot table sizeAaron Durbin
2016-04-21arch/riscv/tables: remove confusion over write_tables()Aaron Durbin
2016-04-21arch/power8/tables: remove confusion over write_tables()Aaron Durbin
2016-04-15bootblock_crt0: Use CR* macros from cpu/x86/cr.hFurquan Shaikh
2016-04-08Change la to li (load immediate)Ronald G. Minnich
2016-04-04arch/power8: Position bootblock start at reset vectorTimothy Pearson
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 19:47:12 +0000