Age | Commit message (Collapse) | Author |
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
furutre, it should be in cpu specific fixup code
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Reworked pnp superio device support. Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes. I've only seen
this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
sensors. Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
is done in cpu_fixup. This is much, much faster.
- Attempted to make the VGA IO region assigment work. The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to
setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
chip.h into the headers of the initialization routines. This is much saner
and is actually implemented.
- Made the hdama port an under clockers BIOS. I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0
TODO finish optimizing the HT links of non dual boards
TODO make all Opteron board work again
TODO convert all superio devices to use the new helpers
TODO convert the via/epia to freebios2 conventions
TODO cpu fixup/setup by cpu type
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
* move acpi to right position
* change acpi checksums
* clean hpet area before creating table
* calculate hpet checksum
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
* initial acpi support code
* fix header
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
* subtractive resources
* merging with the static device tree
* more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
- Updates to config.g so that it works more reliably and has initial support
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
killed src/sdram/generic_dump_spd.inc
killed src/sdram/generic_dump_spd.inc
- Updated the arima/hdama to build with the new configuration system
- Updated config.g to list all of the variables with make echo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Changes to allow more code to be compiled both ways
- Working SMP support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- romcc_io.h Add include guards.
- hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
- auto.c Changed the enabled debugging comments. This almost works with 2 cpus
- coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them
in some semblance of a working state.
- raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
to run out of registers. Use | to be explicit that I don't need the short
circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
with older ones...
- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
code that runs without ram and code that runs with ram.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
The goal is to have the same interface with or without romcc.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Implementation of fallback/normal support for the amd solo board
- Minor bugfix in romcc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
fewer registers, and is easier to hardcode.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
I need a very early Hypertransport setup to get anything more going.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|