summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
2016-12-06riscv: Stub out sbi_(un)mask_interruptJonathan Neuschäfer
2016-12-06arch/riscv/mcall.c: Return the correct memory base and sizeJonathan Neuschäfer
2016-12-01arch/x86: cache postcar in stage cacheAaron Durbin
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
2016-11-28Build system: Update HAVE_CMOS_DEFAULTMartin Roth
2016-11-24arch/x86/acpigen: Write DSM method with multiple UUID'sNaresh G Solanki
2016-11-21arch/x86: don't create new gdt in cbmem for relocatable ramstageAaron Durbin
2016-11-20riscv: map first 4GiB of physical address spaceRonald G. Minnich
2016-11-20arch/x86 GDT: Fix orphan debug outputKyösti Mälkki
2016-11-17arch/x86/acpigen: Implement acpigen functions to return integer & stringNaresh G Solanki
2016-11-17arm64: arm_tf: Do not build raw bl31.bin binaryJulius Werner
2016-11-17arch/x86/acpigen: acpigen buffer size fixNaresh G Solanki
2016-11-16arch/x86/acpigen: Fix acpigen for If (Lequal (...))Furquan Shaikh
2016-11-14riscv: add a variable to control trap managementRonald G. Minnich
2016-11-13riscv: change payload() to pass the config string pointer as arg0Ronald G. Minnich
2016-11-12riscv: start to use the configstring functionsRonald G. Minnich
2016-11-09ACPI S3: Remove HIGH_MEMORY_SAVE where possibleKyösti Mälkki
2016-11-07arch/x86/acpigen: Add OperationRegion & Field methodNaresh G Solanki
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
2016-10-25arch/x86/acpigen_dsm: Add support for DSM typesFurquan Shaikh
2016-10-25arch/x86/acpigen: Add support for _DSM method generationFurquan Shaikh
2016-10-25arch/x86/acpigen: Add more functions to ACPIGEN libraryFurquan Shaikh
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
2016-10-24arch/x86/acpigen: Add support for interacting with GPIOsFurquan Shaikh
2016-10-24arch/x86/acpigen: Add new functions to acpigen libraryFurquan Shaikh
2016-10-24arch/x86/acpigen: Clean up acpigen libraryFurquan Shaikh
2016-10-18arch/riscv: In trap handler, don't print SP twiceJonathan Neuschäfer
2016-10-15arch/riscv: Visually align trap frame informationJonathan Neuschäfer
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
2016-10-15arch/riscv: Remove unused bootblock_simple.cJonathan Neuschäfer
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
2016-10-07src/arch: Remove whitespace after sizeofElyes HAOUAS
2016-10-07x86/acpi_device: Add support for GPIO output polarityFurquan Shaikh
2016-10-07x86/acpi_device: Fix writing of array propertyFurquan Shaikh
2016-10-07RISCV: update the encoding.h file.Ronald G. Minnich
2016-10-06arm64: Use 'payload' format for ATF instead of 'stage'Simon Glass
2016-09-27x86: acpi: Use GOOG ID for coreboot tableDuncan Laurie
2016-09-21x86: acpi: Add function for querying GPE statusDuncan Laurie
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
2016-09-20arm_tf: Fix code style nits and commentsSimon Glass
2016-09-19Revert "x86: acpi: Add function for querying GPE status"Duncan Laurie
2016-09-19x86: acpi: Add function for querying GPE statusDuncan Laurie
2016-09-19arch/x86,lib: make cbmem console work in postcar stageAaron Durbin
2016-09-19arch/x86: move postcar main logic into CAaron Durbin
2016-09-15arch/acpi_ivrs.h: Update 8-byte IVRS entry valuesMartin Roth
2016-09-12src/arch: Improve code formattingElyes HAOUAS
2016-09-12arch/arm: Add armv7-r configurationHakim Giydan
2016-09-12arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrrRizwan Qureshi
2016-09-12arch/x86: Always compile postcar library in romstageRizwan Qureshi
2016-09-07include/arch/acpi.h: change IVRS efr field to iommu_feature_infoMartin Roth
2016-09-07x86/acpi.c: use #define for IVRS revision fieldMartin Roth
2016-09-07arch/x86/include: Add #defines for IVRS tablesMartin Roth
2016-09-04arch/acpi.h: add #if guard to handle the absence of device_t typeAntonello Dettori
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
2016-08-28src/arch: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-28src/arch: Capitalize CPU and ACPIElyes HAOUAS
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer
2016-08-23arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-08-15arch/riscv: Set the stack pointer upon trap entryJonathan Neuschäfer
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
2016-08-06acpi: Generate object for coreboot table regionDuncan Laurie
2016-08-04src/arch/riscv/id.S: Don't hardcode the stringsJonathan Neuschäfer
2016-08-03ACPI: Add code to create root port entry in DMAR tableWerner Zeh
2016-08-03ACPI: Add code to include ATSR structure in DMAR tableWerner Zeh
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-08-01arch/x86: Enable postcar consoleLee Leahy
2016-08-01arch/x86: Display MTRRs after MTRR update in postcarLee Leahy
2016-07-31src/arch: Capitalize CPU, RAM and ROMElyes HAOUAS
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-07-18arch/riscv: Remove enter_supervisorJonathan Neuschäfer
2016-07-18arch/riscv: Change all eret instructions to .word 0x30200073 (mret)Jonathan Neuschäfer
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
2016-07-14arch/riscv: Unconditionally start payloads in machine modeJonathan Neuschäfer
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
2016-07-07acpigen_write_package: Return pointer to package element counterDuncan Laurie
2016-07-02acpi_device: Have acpi_device_scope() use a separate bufferDuncan Laurie
2016-07-02gpio: Add support for translating gpio_t into ACPI pinDuncan Laurie