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2023-07-10vboot: Fix S3 resume with stage_cacheKyösti Mälkki
In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not get called when postcar was loaded from TSEG stage cache on ACPI S3 resume path. Resume failed as MP init attempts to access microcode update from unverified FW_MAIN_A/B section. In a similar fashion, for POSTCAR=n, loading ramstage from TSEG stage cache would bypass the call to vboot_run_logic(). TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able to complete S3 resume. Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-05arch/x86: Ensure LAPIC mode for exception handlerKyösti Mälkki
Attempting to use X2APIC MSRs before the call to enable_lapic() is made raises exception and double-faults. Change-Id: Ib97889466af0fbe639bec2be730784acc015b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-27arch/x86/Kconfig: remove period from DUMP_SMBIOS_TYPE17 titleEric Lai
Option name strings should not end with a period, remove it. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Id61d8961cad2cd311db7d9da3bdb86f0f28b57b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22arch/x86,lib: Migrate SMBIOS implementation to common codeBenjamin Doron
SMBIOS is not specific to architecture, and this is mostly a generic implementation. Therefore, move it to common code, having architecture-specific code define some functions to fill this data. Change-Id: I030c853f83f8427da4a4c661b82a6487938b24e6 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75886 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-06-20arch/x86: Introduce DUMP_SMBIOS_TYPE17 configEric Lai
DDR5 spd is not supported read by coreboot. But FSP can read it, so print the memory information from smbios type17 dimm information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06arch/x86/include/arch/vga: add defines for VGA MMIO addressesFelix Held
To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held
Only the Intel Quark SoC selected this option and that SoC was dropped in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this Kconfig option too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26treewide: Remove 'extern' from functions declarationElyes Haouas
"extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-25arch/x86/include/arch/pci_io_cfg: add IO port count & last port definesFelix Held
The PCI config space access via IO ports uses two 32 bit IO ports. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie99b4f5fc01fb0405243ff108d813ee1a3d35e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75408 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25arch/x86: Don't allow hw floating point operationsArthur Heymans
Even though coreboot does not allow floating point operations some compilers like clang generate code using hw floating point registers, e.g. SSE %XMMx registers on 64bit code by default. Floating point operations need to be enabled in hardware for this to work (CR4). Also in SMM we explicitly need to save and restore floating point registers for this reason. If we instruct the compiler to not generate code with FPU ops, this simplifies our code as we can skip that step. With clang this reduces the binary size a bit. For instance ramstage for qemu/Q35 drops from 216600 bytes decompressed to 212768. TEST: See that with x86_64 bit and clang coreboot reaches the payload without setting the CR4_OSFXSR bit in CR4. Without this change it would bootloop very early in the bootblock on Qemu Q35. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib8590c55e7aed1ece2aa23b8ea99463396435e11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75316 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16x86: pci_io_cfg: Make constant unsigned to fix out of bounds shiftPaul Menzel
Fix the error below when running a coreboot image built with `CONFIG_UBSAN=y`. PCI: pci_scan_bus for bus 00 shift out of bounds src/arch/x86/include/arch/pci_io_cfg.h:13:20 ubsan: unrecoverable error. GCC with `-fsanitize=shift` also flags this: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' So, make the constant unsigned. TEST=emulation/qemu-i440fx with `CONFIG_UBSAN=y` stops later with [ERROR] unaligned access src/lib/rmodule.c:152:27 [EMERG] ubsan: unrecoverable error. Change-Id: Ib05d225ab9f22078d765009b4ee6ef0c63231eed Found-by: UBSAN Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14arch/x86/ioapic.c: Increase the number of bits for ioapic IDArthur Heymans
In practice hardware can use larger numbers. Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-09arch/x86/car.ld: Fix undefined macroArthur Heymans
Processing LD flags is done without most warnings enabled, which is why this never caused problems. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9d82c1426a1c1d2f21c8e7560685cf9d7106a88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75033 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki
Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is setJulius Werner
walkcbfs_asm is a simple CBFS implementation in assembly to find a file on a system with memory-mapped SPI flash. It seems to be mostly unused nowadays and is only still called for early microcode loading on some old systems (e.g. FSP 1.1 and older). Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe because it does not verify the hashes the way the normal CBFS code does. Therefore, to avoid potential security vulnerabilities from creeping in, this patch makes sure the code cannot be compiled in when CBFS_VERIFICATION is active. That means it won't be supported on the old boards using this for microcode loading. Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this dependency more obvious in menuconfig, but the configs actually using this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM is just set everywhere by default although only very few boards are really using it, and a lot of different old Intel CPU models are linking in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under a single Kconfig so that's not easy to change). To keep things simple, this patch will just prevent the code from being built and result in a linker error if a bad combination of Kconfigs is used together. Later patches can clean up the Kconfigs to better wrap that dependency if the affected boards are still of enough interest to be worth that effort. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] defineFelix Held
Instead of having multiple instances of the same magic numbers in the code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA definitions. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/amd: Clarify ACPI _PRT entry generationKyösti Mälkki
The reference to a constant FCH IOAPIC interrupt count used with GNB IOAPIC was a bit obscure. Change-Id: I2d862e37424f9fea7f269cd09e9e90056531b643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-06cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans
It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04arch/x86/smbios: Check str for NULL in smbios_add_string()Maximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73980 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-29arch/x86/smbios: Add socket type for Meteor LakeJay Patel
Add socket type for Meteor Lake as PROCESSOR_UPGRADE_OTHER. BUG=None TEST=processor upgrade is equal to "Other" for "dmidecode -t 4" Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: If891990436a0679697e292b460eaec63c09e7bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-22x86/include/registers.h: macros should not use a trailing semicolonYuchen He
Macros should not use a trailing semicolons. Remove those from 'LONG_DOWNTO8' aswell as 'LONG_DOWNTO16' and add them at places where the macros are used. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I5ba01bc09f9a2d9ecd54014e27ec0a24c7297412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-16arch/x86/ioapic: Print IOAPIC ID for GSI #0Jay Patel
Print IOAPIC ID for GSI #0 in logs, as part of IOAPIC initialization. BUG=None TEST=Confirmed "IOAPIC: ID = 0x00" printed in logs. Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: I8d8e94fe623795d059ec2abbb3319b60fd80f5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/73707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-03-13arch/x86/include/arch/mmio.h: Provide __always_inline definition for muslFabian Groffen
fix compilation on musl-libc systems by providing an implementation for __always_inline Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I01a7eb9ed28e79523623ab362510ec2d93f4a8b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73667 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13cpu/x86/cache: CLFLUSH programs to memory before runningArthur Heymans
When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that these are all in UC memory such that calling INVD in postcar is OK. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR's to make that UC. TESTED on asus/p5ql-em, up/squared on both regular and S3 resume bootpath. Sometimes there are minimal performance improvements when cbmem is cached (few ms). Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-21arch/x86/smbios: use cpu_cpuid_extended_level instead of open coding itFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice15f0ce591104a2ace186f9049748219c2bc097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09treewide: Remove repeated wordsElyes Haouas
Found by linter Change-Id: I7a49cce0b56cf83d0e4490733f9190284a314c4a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-08soc/amd/picasso/soc_util: use cpuid_matchFelix Held
Now that there is a cpuid_match function, we can use it instead of doing basically the same thing manually. In the functions is_fam17_1x and is_fam17_2x both the stepping number and the lower nibble of the model number are masked out. To avoid having magic constants in the code, introduce the CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72860 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08arch/x86/cpu: move cpuid_match to corresponding header fileFelix Held
Since the functionality of cpuid_match is also useful outside of arch/x86/cpu.c and it's a relatively simple function, move its definition as inline function to the header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96746b33b01781543f60cf91904af35418e572d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72859 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08arch/x86/include/cpu: introduce CPUID_FROM_FMS macroFelix Held
Introduce a macro to get the raw CPUID leaf 1 EAX value from a given set of CPU family, model and stepping. The processor type in bits 12 and 13 is assumed to be always be zero; at least this is the case for all CPUIDs that are currently in the coreboot tree. This can be used to make the device values in the CPU device ID tables easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idab77453712b14983b1d02ca365f7924239fc2bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72856 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-08arch/x86/include/cpu: retype device field in cpu_device_idFelix Held
Use a more specific type in preparation for using bit masks on this field in the next patch. Since uint32_t is a typedef of unsigned int, this won't change behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic54f73dcd3496a5ad85291b9b9586bc740b734d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72846 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30arch/x86/smbios.c: Add socket type for Intel SPR-SPChristian Walter
Intel SPR-SP processor has socket type as PROCESSOR_UPGRADE_SOCKET_LGA4677 which is different from the socket type of CPX-SP and SKX-SP. Change-Id: Id2279cc0c1fa3f007d7c081af6f78e5aa98d2f3d Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71947 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29arch/x86/smbios.c: Update Xeon-SP socket typesDavid Hendricks
Now that we support >1 Xeon-SP, XEON_SP_COMMON_BASE no longer reflects the socket type. This uses SOC_INTEL_* Kconfig variables and returns the correct socket type for Cooper Lake-SP. Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I142de5f040f3b76e352f27c00fe9e50787df5712 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-21arch/x86/Kconfig: Remove unused NUM_IPI_STARTSElyes Haouas
Change-Id: I3b781c42ef6c23a5dcd31215c14fb9d7104822f2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21arch/x86/include: Remove unused <stddef.h>Elyes Haouas
Change-Id: I2a4b00d06c92eea1b83002c69d93037f84592393 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72111 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk
TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08arch/x86/smbios: Replace SMBIOS type4 processor upgrade fieldsLi, Jincheng
values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25arch/x86: Use 'enum cb_err'Elyes Haouas
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-23cpu/x86: Set up a separate stack for APsArthur Heymans
APs use a lot less stack, so set up a separate stack for those in .bss. Now that CPU_INFO_V2 is the only code path that is used, there is no need to align stacks in c_start.S. Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-17lib: Hook up libhwbase in romstageJeremy Compostella
It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'. This also adds some glue code to use the coreboot console for debug output and our monotonic timer framework as timer backend. Running Ada code in romstage and more particular libhwbase brings a few challenges as global initialized variables are not supported in Cache-As-Ram mode. 1. The libhwbase dynamic mmio driver implementation makes the Gnat compiler generate some global initialized variables. For this reason, when compiled for romstage or for romstage and ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO'). 2. The Gnat compiler generates elaboration functions to initialize program data at runtime. These elaboration functions are called by the romstage_adainit() function. The data references symbols suffixed by `_E'. Even though these symbols, at compilation time, do not contain any data and are filled with zeros, the Gnat compiler installs them in the .data section. Since these symbols are actually filled with zeros, it is safe to install them in the .bss section. cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_order_handling_in_gnat.html#elaboration-code This patch requires the libhwbase https://review.coreboot.org/c/libhwbase/+/69854 CL. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libhwbae compiles for romstage and loads successfully Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70275 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16Set x86_64 as supported architecture for clangArthur Heymans
This boots on both qemu and real hardware now. Change-Id: Ibd320059cff575847bbf1844b5bb100312f77916 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-10cpu/cpu.h: Change the function signatureArthur Heymans
There is no need to pass the CPU index around. Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-07arch/x86/ioapic.c: Move macros to compilation unitArthur Heymans
Some of these macros are too generic like "NONE" and create conflicts in other compilation units. Change-Id: I6131a576f115df20df4d3df712d4c3f59c6dceb7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70429 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06arch/x86/smbios.c: Allow creating entries for empty DIMM slotsAngel Pons
Properly handle meminfo DIMMs with `dimm_size` of 0, which represent empty slots. This allows platform code to create dummy meminfo DIMMs so that SMBIOS tables have type 17 entries for empty DIMM slots. Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64035 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30arch/x86: Buildtest clang targets with VBOOT_STARTS_BEFORE_BOOTBLOCKArthur Heymans
TESTED: google/vilboz boots with clang build. Change-Id: Ie115c27b4cb0b8f83d7647bdd27ffcbac9376399 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69746 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30/: Remove extra space after commaElyes Haouas
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29Revert "src/arch/x86: Use core apic id to get cpu_index()"Arthur Heymans
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13. Previously cpu_info() was implemented with a struct on top of an aligned stack. As FSP changed the stack value cpu_info() could not be used in FSP context (which PPI is). Now cpu_info() uses GDT segments, which FSP does not touch so it can be used. This also exports cpu_infos from cpu.c as it's a convenient way to get the struct device * for a certain index. TESTED on aldrvp: FSP-S works and is able to run code on APs. Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/arch: Remove unnecessary space after castsElyes Haouas
Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69816 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17arch/x86/smbios: Add SMBIOS Type 39Jonathan Zhang
Read FRU product info of PSU to get Type 39 required information. Further development needed if multi-record info of PSU FRU is required. For now, the read_fru_areas() only read product chassis and board info. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Signed-off-by: ziang <ziang.wang@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I18d056cba1a79b0775c8a42b3a879e819887adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-11-16arch/x86: Disable clang build if using verstage_before_bootblockMartin Roth
Clang isn't working so well with the ARM code yet. This is still breaking builders after fixing the compiler warnings. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69701 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-14arch/x86/Kconfig: Move AMD stages arch to common codeArthur Heymans
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-13arch/x86/mpspec.c: Drop weak write_smp_table()Kyösti Mälkki
Creating MP table is not useful when it does not include the interrupt routing entries. Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69489 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13drivers/generic/ioapic: Drop poor implementationKyösti Mälkki
This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12arch/x86/memmove: Add 64bit versionArthur Heymans
The 64bit handles 64bit input variables properly. TESTED: Both qemu and real hardware can use LZ4 properly which use this code. Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12cpu/x86: Set thread local storage in C codeArthur Heymans
Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69435 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10arch/x86/ioapic: Reduce API exposureKyösti Mälkki
Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55316 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10arch/x86: Add register_new_ioapic()Kyösti Mälkki
Using this I/O APIC IDs will be assigned incrementally in the order of calling. I/O APIC ID #0 is reserved for the I/O APIC delivering GSI #0. Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-08arch/x86 & commonlib: Add macros for postcodes used in x86/tablesMartin Roth
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the coreboot tree other than in arch/x86/tables.c. Add macros to standardize these postcodes. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-07cpu/x86: Drop !CPU_INFO_V2 codeArthur Heymans
Now that all platforms use parallel_mp this is the only codepath used for cpu_info() local thread storage. Change-Id: I119214e703aea8a4fe93f83b784159cf86d859d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69122 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07cpu/amd/agesa: Remove leftover codeArthur Heymans
Now that all agesa CPUs are removed this code is unused. Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03treewide: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-26arch/x86: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-24arch/x86: x86_64 implies SSE2 supportPatrick Rudolph
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume SSE2 is present and enabled when targeting x86_64. This fixes: - lzma decompression code is compiled with the -Ofast flag - 'everything' when compiling with clang. This mostly affects qemu targets, which did not have this flag selected yet. TESTED on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-22arch/x86/include/arch: fix assembly clobber for 64bitMatei Dibu
the "x86 PIC code ebx" workaround done previously by commit 689e31d18b0f ("Make cpuid functions usable when compiled with PIC") does not work for x86_64 (the upper dword of rbx is set to 0) the GCC bug that needed the workaround was fixed in version 5 (see GCC bug 54232) Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95 Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-20arch/x86/include: Split CPUID access into separate fileMartin Roth
To allow testing of code that uses CPUID calls, separate the actual calls into a separate header file, This allows the tests to emulate the cpuid access without replacing the rest of the cpu.h definitions. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20arch/x86: Only use .bss from car.ld when running XIPArthur Heymans
Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. This make in place LZ4 decompression possible as it needs a bit of extra place to extract the code which is now provided by the .bss. Tested on up/squared (Intel APL). Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-10-17arch/x86/smbios.c: Fix Upgrade processor information in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements upgrade function. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor upgrade value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-06smbios: Add API to generate SMBIOS type 28 Temperature ProbeErik van den Bogaert
Based on DMTF SMBIOS Specification 3.5.0 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06arch/x86/timestamp.c: Add missing <stdint.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6870fb9f3d41ef5dc6599e979ce0c890a1e145ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06arch/x86/mmap_boot.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I85e60c189c1ec1da5cf0e5b864447ef6f7b3f548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-30smbios: Add API to generate SMBIOS type 43 TPM DeviceMichał Żygowski
Based on DMTF SMBIOS Specification 3.1.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-09-29treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto
use is_enabled_cpu() on cycles over device list to check whether the current device is enabled cpu. TEST: compile test and qemu run successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-29arch/x86/idt.S: Use 'iretq' for ENV_X86_64Elyes HAOUAS
Fix the warning below when building GA-945GCM-S2L with 64-bit: src/arch/x86/idt.S:216: Warning: no instruction mnemonic suffix given and no register operands; using default for `iret' Change-Id: Ibbc106714e25293951a71d84fea0a660f41f9c02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26x86: Zero SMBIOS region before writing tablesJonathon Hall
Clear the SMBIOS region before writing SMBIOS tables. On librem_mini and librem_mini_v2, CBMEM allocations are offset by 4K for reboots relative to the cold boot. This means the unused SMBIOS region could contain the first 4K of the ACPI tables from the last boot (including the signature), which prevents Linux from booting. The CBMEM 4K offset appears to be due to FSP allocating memory differently between cold boot and reboot, this appears to be normal and causes the CBMEM base address to change. It is not clear why Linux examines an ACPI signature found in this region, but boot logs over serial confirm that it sees the corrupt table. The table is supposed to be found just below 1M, and kernel source appears to look in this region, but it is definitely finding the corrupt table in CBMEM. Normal cold boot: [ 0.008615] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008619] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008624] ACPI: FACP 0x0000000099B4A2A0 000114 (v06 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008634] ACPI: DSDT 0x0000000099B48280 00201F (v02 COREv4 COREBOOT 20110725 INTL 20220331) ... Reboot with corrupt table: [ 0.008820] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4) [ 0.008823] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331) [ 0.008828] ACPI: ???G 0x0000000099B4A2A0 20002001 (v00 ?G?$ 47020100 ?, 47020100) [ 0.008831] ACPI: �y 0x0000000099B4A3C0 54523882 (v67 ?_HID? A�? 65520D4E al T 20656D69) ... There are no specific errors but it returns to the firmware soon after, presumably due to a fault. This appears to be so early in the boot that panic=0 on the kernel command line has no effect. Test: build/boot Librem Mini, Librem Mini v2 and reboot. Change-Id: Ia20d0b30160e89e8d96add34d7e0e881f070ec61 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66377 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-24src/arch/x86/smbios.c: remove unneeded bracesFabio Aiuto
fix the following checkpatch errors: WARNING:BRACES: braces {} are not necessary for any arm of this statement 354: FILE: src/arch/x86/smbios.c:354: + if (CONFIG_ROM_SIZE >= 1 * GiB) { [...] + } else { [...] WARNING:BRACES: braces {} are not necessary for single statement blocks 561: FILE: src/arch/x86/smbios.c:561: + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-30arch/x86/acpi: Replace Store() with ASL 2.0 syntaxFelix Singer
Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-30arch/x86/acpi: Replace And() with ASL 2.0 syntaxFelix Singer
Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-30arch/x86/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: If0e9fcea680d487c28a965e944b3333bb5a07026 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60696 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-30arch/x86/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ief1d069ae0fb19a2179f08c2e9cf416367661e69 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60674 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: If848d391e5ec33ebfb08515414739dbdd5011e08 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-07-20arch/x86/*.ld: Don't use CPP to include linker scriptsArthur Heymans
This makes inspection of linker scripts in the build dir a little easier. Change-Id: I509faa4cee2c9f066f4e20f6038349e1165a619a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas
Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-14arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans
This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntaxFelix Singer
Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntaxFelix Singer
Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-07arch/x86: Add a common romstage entryArthur Heymans
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-03arch/x86/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I0cabf4f69191fe345fd72619847db384db2e0e87 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 06:07:39 +0000