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2012-04-16S3 code in coreboot public folder.zbao
1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16ACPI HEST table.zbao
HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/888 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-12Unify IO APIC address specificationPatrick Georgi
Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-08Actually return %ebx value from cpuid_ebx()Jonathan A. Kollasch
Change-Id: I75f8f942950cad94439a10e389490ecfdd9272fe Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300 Only align 16-bit entry on platforms that really require it, indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of AP_SIPI_VECTOR for platforms not depending on this feature. Build of romstage should be fixed to get the vector address from bootblock build automatically. Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Factor out function to find driver for a CPUStefan Reinauer
This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/868 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05smbios: Don't fill out firmware version on ChromeOSStefan Reinauer
In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/867 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Fill out ChromeOS specific coreboot table extensionsStefan Reinauer
ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/866 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Use fast memset in SMM mode, tooStefan Reinauer
... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/827 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support for mainboard specific suspend/resume handlerStefan Reinauer
Some mainboards (most likely laptops) will need mainboard specific functions called upon a resume from suspend. Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Drop verified boot code from acpi.cStefan Reinauer
We changed our verified boot initialization to run from romstage, as that allows faster boot times and does not add as much ChromeOS specific code to generic files. Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/607 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Fix issues with x86 memcpyMathias Krause
The x86 memcpy() implementation did not mention its implicit output registers ESI, EDI and ECX which might make this code miscompile when the compiler uses the value of EDI for the return value *after* the 'rep movsb' has completed. That would break the API of memcpy as this would return 'dst+len' instead of 'dst'. Fix this possible bug by removing the wrong comment and listing all output registers as such (using dummy stack variables that get optimized away). Also the leading 'cld' is superflous as the ABI mandates the direction flag to be cleared all the time when we're in C (see <http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites that might require it to be cleared explicitly (SMM might come to mind, but it clears the DF itself before passing control to the C part of the SMI handler). Last but not least fix the prototype to match the one from <string.h>. Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/836 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-31Add support for RAM-less multi-processor initKyösti Mälkki
For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/454 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31Makefile: rename romstage linking filenamesKyösti Mälkki
$(obj)/location.txt -> $(obj)/romstage/base_xip.txt $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/812 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Makefile: split romstage linking to separate rulesKyösti Mälkki
After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/803 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31Fix coreboot makefiles not to produce half baked output.Kyösti Mälkki
There were cases where output file was generated and modified within a recipe. If make was interrupted, it could exit with an output file that appears as up-to-date, but was generated with incomplete recipe. The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-30use movsl for copying resume memory backStefan Reinauer
It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/755 Reviewed-by: Mathias Krause <minipli@googlemail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Don't re-init EBDA in S3 resume path.Duncan Laurie
I forgot to implement this the first time around. It does not seem to cause noticeable problems but in heavy suspend/resume testing I saw a suspicious crash in the kernel when trying to bring one of the CPUs back online. Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Prepare the BIOS data areas before device init.Duncan Laurie
Since we do not run option roms in normal mode nothing was initializing the BDA/EBDA and yet Linux depends very much on it having sane values here. For the most part the kernel tries to work around this not being initialized, but every once in awhile (1/300 boots or so) it would end up reading something that looked sane from BDA but was not and then it would panic. In this change the EBDA is unconditionally setup before devices are initialized. I'm not set on the location in dev_initialize() but there does not seem to be another place to hook it in so that it runs just once for ALL platforms regardless of whether they use option roms or not. (possibly hardwaremain?) The EBDA setup code has been moved into its own location in arch/x86/lib/ebda.c so it can be compiled in even if the option rom code is not. The low memory size is still set to 1MB which is enough to make linux happy without having to hook into each mainboard to get a more appropriate value. The setup_ebda() function takes inputs so it could be changed for a mainboard if needed. OLD/BROKEN would read garbage. Examples from different boots: ebda_addr=0x75e80 lowmem=0x1553400 ebda_addr=0x5e080 lowmem=0x3e51400 ebda_addr=0x7aa80 lowmem=0x2f8a800 NEW/FIXED now reads consistent values: ebda_addr=0xf6000 lowmem=0x100000 Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/769 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Make cpuid functions usable when compiled with PICDuncan Laurie
This avoids using EBX and instead uses EDI where possible, and ESI when necessary to get the EBX value out. This allows me to enable -fpic for SMM TSEG code. Also add a new CPUID extended function to query with ECX set. Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/764 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-30Make PCI CONF2 support a compile time optionStefan Reinauer
It's not used on any board supported by coreboot but has been detected at run time since ages. No new boards (since 2000?) are using the CONF2 method, so it is unlikely we ever have to turn this on for a board. Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/758 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add more timestamps in coreboot.Stefan Reinauer
This adds a number of timestamps in ramstage and romstage so we can figure out where execution time goes. Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/749 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Fix coreboot makefiles not to produce half baked output.Vadim Bendebury
It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-03-30Add timestamps for selfboot and acpi wakeDuncan Laurie
Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add TPM support to corebootStefan Reinauer
and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add an option to keep the ROM cached after romstageStefan Reinauer
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add native memset() function on x86Stefan Reinauer
Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/737 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-30Add faster, architecture dependent memcpy()Stefan Reinauer
Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/736 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-29Add infrastructure for global data in the CAR phase of bootGabe Black
The cbmem console structure and car global data are put in their own section, with the cbmem console coming after the global data. These areas are linked to be where CAR is available and at the very bottom of the stack. There is one shortcoming of this change: The section created by this change needs to be stripped out by the Makefile since leaving it in confuses cbfstool when it installs the stage in the image. I would like to make the tools link those symbols at the right location but leave allocation of that space out of the ELF. Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-29Detect whether the OXPCIE card is really present while in the ROM stage.Gabe Black
Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/728 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury
We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/724 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Add timestamp table pointer to the coreboot table.Vadim Bendebury
This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29CBMEM CONSOLE: Add code using the new console driver.Vadim Bendebury
The new added code is compiled in when the CBMEM_CONSOLE config flag is enabled. Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/721 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-25Makefile: rename linker intermediate variableKyösti Mälkki
Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig. Removed no-op calculation in ldscript. Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/802 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-20Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 ↵Rudolf Marek
class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/683 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-17Another indirection for normal/fallback bootblockPatrick Georgi
Provide a way to redefine the names of normal and fallback via CBFS. This way updates can use some more expressive naming scheme (numbers, dates, version numbers) and replace the coreboot-stages file to point to the new version (with the current version as new "old"). If coreboot-stages doesn't exist, the default behaviour remains to use "normal" and "fallback". Change-Id: I77c134d79ed95831ad5098b7663c15e95d3b5a2a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/589 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/792 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16Use search path when building dependenciesPatrick Georgi
clang is more picky on that. Change-Id: Iaa8472beb6e275c39037d11e1a72dbb80d46424b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-16Via Epia-N and C3: Set ioapic delivery type in KconfigPatrick Georgi
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins)
2012-03-11No need to setup include paths with .s filesPatrick Georgi
They're already preprocessed, and clang whines. Change-Id: I57fe936f84a2fe1aa50ee8510fef606f2ed2ea23 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/782 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-10If the memory mapped UART isn't present, leave it out of the cb tables.Gabe Black
This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/729 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-03-09Increase size of the coreboot table areaStefan Reinauer
Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/704 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix compilation when USE_OPTION_TABLE is not defined.Duncan Laurie
Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/702 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix coreboot table size calculations.Vadim Bendebury
The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/703 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Clean up use of CONFIG_ variables in coreboot_table.cStefan Reinauer
CONFIG_ variables are used inconsistently within the file src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong thing if the option is disabled. #if (CONFIG_FOO == 1) is not needed. Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/701 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-29Fix x86 cpu_phys_address_sizeKyösti Mälkki
After CPUID, requested feature flag is in edx, not eax. Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/688 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-02-17Exit building if romstage.bin is larger than size of XIPzbao
When the romstage.bin becomes bigger than the size of XIP, the cbfstool can not allocate the romstage in the CBFS. But it doesn't report an error. It will take quite a while to find out the root cause. Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/650 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-07Move SeaBIOS output out of coreboot source treeStefan Reinauer
Make sure SeaBIOS build files live under $(OUT) instead of in the source tree. Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/552 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-31X86: fix cpu_phys_address_size()Sven Schnelle
CPUs with CPUID level >= 0x80000008 can return the number of physical address bits. Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/599 Tested-by: build bot (Jenkins)
2012-01-26pci_ops_mmconf: Move conditional compilation to MakefileVikram Narayanan
Moved the conditional compilation out of the source file Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/578 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-24pci_ops_conf: Indentation fixesVikram Narayanan
Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c Change-Id: I56e8ff6d2ee3a0b871b40577e10c99dea4b3b1bd Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/576 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-24pci_ops_mmconf: Indentation fixesVikram Narayanan
Indentation fixes in src/arch/x86/lib/pci_ops_mmconf.c Change-Id: If8337bae06295db16ed1c129ab76dea37eb465ae Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/577 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX instructions in the CPU after romstage. Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/553 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-18Add coreboot version to id areaPatrick Georgi
There was no good way to extract the build version from an image. This change will be mostly backward compatible: The only assumption that could break is that the board name string ends directly before the 3 dwords that represent .id's "header". Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/537 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
The current code uses static values for the physical address size supported by a CPU. This isn't always the right value: I.e. on model_6[ef]x Core (2) Duo CPUs physical address size is 36, while Xeons from the same family have 38 bits, which results in invalid MTRR setup. Fix this by getting the right number from CPUID. Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
This function prevents the linker from choosing the right get_cst_entries(), preventing writing the _CST tables. Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821 Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/496 Tested-by: build bot (Jenkins)
2011-12-24Only BSP CPU writes CMOS in bootblock codeKyösti Mälkki
CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. AP CPUs should always select the same romstage prefix as BSP CPU. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-08Fix ldscript for bootblock .rom sectionKyösti Mälkki
Allocation size for the section was miscalculated, so the section did not honour its upper-bound address. Also align the section start to 4 bytes, so it starts with code instead of pad bytes. Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/453 Tested-by: build bot (Jenkins) Reviewed-by: Alec Ari <neotheuser@ymail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
Relocate early post_code() so it gets executed and does not corrupt BIST at %eax. Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-06Inline Makefile.bootblock.incPatrick Georgi
This was split out when we had separate rules for big bootblock. Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-29Fix coreboot updatesPatrick Georgi
The rule to prepare a new coreboot.pre1 was ignored in the "update image" scenario because a perfectly fine file exists. Mark it phony to fix it. Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/351 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Move linux 2.6.11 workaround to generic codePatrick Georgi
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
Change-Id: Idb4b57044808918de343d31519768d0986840f01 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25ACPI: Add function for writing _CST tablesSven Schnelle
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/312 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21Add macros for 64bit byte order swappingStefan Reinauer
Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-19IOAPIC: fix bitmaskKyösti Mälkki
APIC ID is bits 27..24, not 19..16. Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/299 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19Drop eh_frame instead of moving it into the image.Stefan Reinauer
That's what SeaBIOS does, too, and it works just fine. Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/269 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-15cbfs_and_run_core() is not part of the API, make it static.Stefan Reinauer
It's only used in cbfs_and_run.c Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/273 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-10-15reformat Makefile.bootblock.inc (>80 lines per char)Stefan Reinauer
Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/274 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6Stefan Reinauer
Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13Prevent build breakage without consoles enabledStefan Reinauer
If all console types are disabled, coreboot will fail to compile because static code is unused. This patch fixes the issue. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2 Reviewed-on: http://review.coreboot.org/260 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13refactor vesa mode setting code and bootsplash codeStefan Reinauer
- adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/256 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix romstage creation with gcc 4.6 and CAR targetsStefan Reinauer
newer gcc versions generate ".section .text" instead of just ".text" in their assembler output. This patch makes sure that we don't end up with a superfluous ".section" that makes the build fail. Add -Wno-unused-but-set-variable to CFLAGS if the flag exists. Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/252 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-12Do full flush on uart8250 only at end of printk.Kevin O'Connor
The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-on: http://review.coreboot.org/90 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-07-02whitespace-only changes in acpi.c, replaced spaces with tabsCristian Măgherușan-Stanciu
Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/74 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-06-22Add the coreboot config to CBFSCristian Măgherușan-Stanciu
The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/46 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-05-23We don't have pausing versions of single-IO instructions.Stefan Reinauer
Hence remove the wrong comment. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20Simplify coreboot's console/console.hStefan Reinauer
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c - rename arch/x86/lib/printk_init.c to .../romstage_console.c - drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there should not be any side effects to eliminating another indirection. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Recently the 3 projects using the new AMD reference code have beenScott Duplichan
failing the check for globals (or statics) in romstage. This causes ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the message "Do not use global variables in romstage". The message is working as intended. It is detecting data declared as 'static' when 'static const' was intended. The code executes correctly because it never tries to modify the data. To make reference code updates easy, it is probably best to avoid modifying the AMD provided code if possible. The following change bypasses the "Do not use global variables in romstage" check for the AMD reference code only. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-16bootblock updates: ↵Stefan Reinauer
- allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15sorry for breaking the tree. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 08:46:21 +0000