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2023-04-04arch/x86/smbios: Check str for NULL in smbios_add_string()Maximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73980 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-29arch/x86/smbios: Add socket type for Meteor LakeJay Patel
Add socket type for Meteor Lake as PROCESSOR_UPGRADE_OTHER. BUG=None TEST=processor upgrade is equal to "Other" for "dmidecode -t 4" Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: If891990436a0679697e292b460eaec63c09e7bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-21arch/x86/smbios: use cpu_cpuid_extended_level instead of open coding itFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice15f0ce591104a2ace186f9049748219c2bc097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30arch/x86/smbios.c: Add socket type for Intel SPR-SPChristian Walter
Intel SPR-SP processor has socket type as PROCESSOR_UPGRADE_SOCKET_LGA4677 which is different from the socket type of CPX-SP and SKX-SP. Change-Id: Id2279cc0c1fa3f007d7c081af6f78e5aa98d2f3d Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71947 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29arch/x86/smbios.c: Update Xeon-SP socket typesDavid Hendricks
Now that we support >1 Xeon-SP, XEON_SP_COMMON_BASE no longer reflects the socket type. This uses SOC_INTEL_* Kconfig variables and returns the correct socket type for Cooper Lake-SP. Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I142de5f040f3b76e352f27c00fe9e50787df5712 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-08arch/x86/smbios: Replace SMBIOS type4 processor upgrade fieldsLi, Jincheng
values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-06arch/x86/smbios.c: Allow creating entries for empty DIMM slotsAngel Pons
Properly handle meminfo DIMMs with `dimm_size` of 0, which represent empty slots. This allows platform code to create dummy meminfo DIMMs so that SMBIOS tables have type 17 entries for empty DIMM slots. Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64035 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17arch/x86/smbios: Add SMBIOS Type 39Jonathan Zhang
Read FRU product info of PSU to get Type 39 required information. Further development needed if multi-record info of PSU FRU is required. For now, the read_fru_areas() only read product chassis and board info. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Signed-off-by: ziang <ziang.wang@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I18d056cba1a79b0775c8a42b3a879e819887adca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-11-09Revert "mb/aopen/dxplplusu: Remove board"Kyösti Mälkki
This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e and applies minor fixes to make it build again. PARALLEL_MP was working prior to board removal and no relevant SMI handlers were implemented. So NO_SMM choice is now selected. Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-07mb/aopen/dxplplusu: Remove boardArthur Heymans
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17arch/x86/smbios.c: Fix Upgrade processor information in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements upgrade function. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor upgrade value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-06smbios: Add API to generate SMBIOS type 28 Temperature ProbeErik van den Bogaert
Based on DMTF SMBIOS Specification 3.5.0 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30smbios: Add API to generate SMBIOS type 43 TPM DeviceMichał Żygowski
Based on DMTF SMBIOS Specification 3.1.0. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-08-24src/arch/x86/smbios.c: remove unneeded bracesFabio Aiuto
fix the following checkpatch errors: WARNING:BRACES: braces {} are not necessary for any arm of this statement 354: FILE: src/arch/x86/smbios.c:354: + if (CONFIG_ROM_SIZE >= 1 * GiB) { [...] + } else { [...] WARNING:BRACES: braces {} are not necessary for single statement blocks 561: FILE: src/arch/x86/smbios.c:561: + if (leaf_b_threads == 0) { + leaf_b_threads = 1; + } Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-05-28arch/x86/smbios.c: Fix for CONFIG_MAX_CPUS > 255Arthur Heymans
Change-Id: I079c99006fea95ba3dc2fb02c95a3747af55e218 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04SMBIOS/SCONFIG: Allow devtree-defined Type 41 entriesAngel Pons
Introduce the `smbios_dev_info` devicetree keyword to specify the instance ID and RefDes (Reference Designation) of onboard devices. Example syntax: device pci 1c.0 on # PCIe Port #1 device pci 00.0 on smbios_dev_info 6 end end device pci 1c.1 on # PCIe Port #2 device pci 00.0 on smbios_dev_info 42 "PCIe-PCI Time Machine" end end The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using this syntax to control the generated Type 41 entries. When this option is enabled, Type 41 entries are only autogenerated for devices with a defined instance ID. This avoids having to keep track of which instance IDs have been used for every device class. Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not enabled will result in a build-time error, as the syntax is meaningless in this case. This is done with preprocessor guards around the Type 41 members in `struct device` and the code which uses the guarded members. Although the preprocessor usage isn't particularly elegant, adjusting the devicetree syntax and/or grammar depending on a Kconfig option is probably even worse. Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-21arch/x86/smbios: Add support for wake-up type in smbios type 1Tim Chu
Add system wake-up type in smbios type 1 - system information. TESTED=On S9S, can override original value and show expected result using "dmidecode -t 1". Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: If79ba65426f1f18ebb55a0f3ef022bee83c1a93b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-10-15arch/x86/smbios: Add generation of type 20 tableMatt DeVillier
If available, use data from MEMINFO CBMEM table and saved handles from type 17/19 tables to generate type 20 (Memory Device Mapped Address) SMBIOS table. Windows 10/11 and some other OSes use this table to report the total memory available on a given device. Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58271 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13SMBIOS: Skip `get_smbios_data` for disabled devicesAngel Pons
If a device is disabled, do not call the `get_smbios_data` code. Change-Id: I8960f869e0864f7c82d5fe507f96b62cbd045569 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13SMBIOS: Allow skipping default SMBIOS generationAngel Pons
The call to the `get_smbios_data` device operation is followed by calls to unconditional default functions, which lacks flexibility. Instead, have devices that implement `get_smbios_data` call these default functions as needed. Most `get_smbios_data` implementations are in mainboard code, and are bound to the root device. The default functions only operate with PCI devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so calling these functions for non-PCI devices is unnecessary. QEMU also implements `get_smbios_data` but binds it to the domain device, which isn't PCI either. Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-05smbios.c: Rename two local functionsAngel Pons
Rename two functions that have `walk` in their name but do not perform any walk. The new names are derived from the comments just above these functions' definitions. Also, remove these now-redundant comments. Change-Id: I380a5b60b3f4e820e8f6d6f960826de97c0446be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57361 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03arch/x86: Update debug message to callout the reason for failureSubrata Banik
This patch updates debug message to specifically the case when SMBIOS table 7 write would abort due to either `unknown` CPU or CPU `doesn't have support for deterministic cache cpuid leaf`. Change-Id: I288593b3f78ab858bf66c689e7cfb6ba2ff746d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-03arch/x86: Check unsupported CPU type while writing to SMBIOS table 7Subrata Banik
Don't attempt to fill the SMBIOS table if the CPU doesn't support deterministic cache CPUID. TEST=Able to fix the hang issue seen on ASRock E350M1 with commit hash e2b5fee. Change-Id: Id65dc963e235f7080370a32cf69bcc4bee94d28f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57306 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31smbios.c: Move function definition near call-siteAngel Pons
The `smbios_get_device_type_from_dev()` function is only called once from the `smbios_walk_device_tree_type41()` function. Put the former function's definition above the latter function's, instead of having them a thousand lines apart. Change-Id: Idc6175324ca8a14841eaf7d6904712efb75f2d26 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57205 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-11arch/x86: smbios write 7 table using deterministic cache functionsSubrata Banik
This patch makes use of deterministic cache helper functions, for example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper functions from arch/x86/cpu_common.c file. Also, changed argument for get_number_of_caches() function that receives cpu_get_max_cache_share() data directly. Drop unused variables partitions, cache_line_size and number_of_sets as struct cpu_cache_info.size would provide the cache size directly. TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output. Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0005, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 288 kB Maximum Size: 288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Data Associativity: 12-way Set-associative Handle 0x0006, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE1 Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 192 kB Maximum Size: 192 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE2 Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Unknown Location: Internal Installed Size: 1280 kB Maximum Size: 1280 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: Unknown Handle 0x0008, DMI type 7, 27 bytes Cache Information Socket Designation: CACHE3 Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 12288 kB Maximum Size: 12288 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unified Associativity: 12-way Set-associative Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_full_table_len` functionAngel Pons
Introduce the `smbios_full_table_len` function to consolidate table length calculation. The case where the length of a table equals the length of the structure happens when a table has no strings. Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c Move calculation next to usageAngel Pons
Change-Id: I949da86605e76b186ef2fdbfbc112b71544b694a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_carve_table` functionAngel Pons
Factor out some boilerplate code into a helper `smbios_carve_table` function, which zeroes out the table memory and fills in the header fields common to all tables. Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01arch/x86/smbios.c: Trim some `len` variablesAngel Pons
Reduce the scope or remove some `len` variables. This is done to ease replacing `sizeof` on struct types in a follow-up commit, by ensuring that all to-be-replaced appearances follow the variable declarations. Change-Id: Ied38fcaf87ef5b1e4f93076b4ba2898ad1f98a72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22arch/x86/smbios: Let SMBIOS type 9 be able to write slot IDJingleHsuWiwynn
The slot ID can be passed in from the function caller but parsing slot ID from devicetree is not yet supported and would still be 0. Add Slot ID in SMBIOS type 9 for Delta Lake. Tested=Execute "dmidecode -t 9" to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01mb/ocp/deltalake: Fill ECC type in romstageAngel Pons
Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27arch/x86/smbios: Update SMBIOS type 17 asset tagTim Chu
Add SMBIOS type 17 asset tag. Use dimm locator as default value. Tested=Execute "dmidecode -t 17" to check asset tag field is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph
Move SPD manufacturer ID decoding to device/dram. Will be used by the following patch outside of SMBIOS scope as well. Change-Id: Iec175cd6ab1d20761da955785e4bc0e87ae02dbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07arch/x86/smbios: Add missing guardRaul E Rangel
smbios_type0_bios_version is only defined if HAVE_ACPI_TABLES is set. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I626ab954496833f46d6a785d92cc3b7e7d87e165 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05arch/x86/smbios: Correct SMBIOS type 4 max speedTim Chu
Now smbios type 4 max speed field will use the maximum speed of processor itself if CPUID value can be accessed. However, this field should be the maximum processor speed supported by the system. Here we use smbios_cpu_get_max_speed_mhz only to get correct value. Tested=Execute "dmidecode -t 4" to check max speed is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01arch/x86/smbios: Add Number Of Power Cords field to be overridenJingleHsuWiwynn
For SMBIOS type 3, add function to override number of power cords Tested=Exectute dmidecode -t 3 to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28arch/x86/smbios: Update SMBIOS type 16 Extended Maximum CapacityTim Chu
Update Extended Maximum Capacity field in SMBIOS type 16 so that maximum dimm size can be over 2TB. Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-19arch/x86/smbios: Update SMBIOS type 17 type detailTim Chu
Update SMBIOS type 17 type detail. Define this field by module type. Tested=Execute "dmidecode -t 17" to check type detail is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I6700056edad5db2b86f6da526329b1343b026385 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-01-18ChromeOS: Refactor SMBIOS type0 bios_version()Kyösti Mälkki
Pointer to an empty string (filled with spaces) is stored inside GNVS. Rearrange things to avoid having <chromeos/gnvs.h> in SMBIOS code. Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49281 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10arch/x86/smbios.c: Fix compilation on x86_64Patrick Rudolph
Change-Id: I07780f9a6fa577d7b6bb63884071a7e1ce1bdbfa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-25arch/x86/smbios: Update SMBIOS type 16 error correction typeTim Chu
Add weak function for SMBIOS type 16 error correction type. Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47508 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22cpu/intel/common: Fill cpu voltage in SMBIOS tablesPatrick Rudolph
Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-16arch/x86/smbios: Update memory_array_handle for SMBIOS type 19Tim Chu
Update memory array handle for SMBIOS type 19. TEST=Execute "dmidecode -t 19" to check if memory array handle is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I49078b870bac3c6162913b91651ec09632800f1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26arch/x86/smbios: Populate SMBIOS type 7 with cache informationMorgan Jang
SMBIOS has a field to display the cache size, which is currently set to UNKNOWN unconditionally, multiply the cache size of L1 and L2 by the number of cores. TEST=Execute "dmidecode -t 7" to check if the cache information is correct for Deltalake platform Change-Id: Ieeb5d3346454ffb2291613dc2aa24b31d10c2e04 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12arch/x86/smbios: Update SMBIOS type 0 ec versionTim Chu
Update embedded controller firmware version for SMBIOS type 0. TEST=Execute "dmidecode -t 0" to check if the ec version is correct Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12arch/x86/smbios: Update SMBIOS type 4 socket designationTim Chu
Add socket designation in type 4 smbios. TEST=Execute "dmidecode -t 4" to check if the socket designation is correct Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28arch/x86/smbios: Add SMBIOS Thread CountFrancois Toguo
Add Thread Count in SMBIOS type 4 "Processor Information". Modify Thread Count 2 according to SMBIOS spec, it should be the number of threads per processor socket. TEST="dmidecode -t4" to check. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-03memory_info: add max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is ambiguous and is interpreted differently in several places. Instead of renaming this field, this deprecates it and adds two new fields with unambiguous naming, max_speed_mts and configured_speed_mts. smbios.c falls back to using ddr_frequency when either of these fields are 0. The same value was being used for both configured memory speed and max memory speed in SMBIOS type 17, which is not accurate when configured speed is not the max speed. BUG=b:167218112 TEST=Boot ezkinil, no change to dmidecode -t17 Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44549 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31mb/ocp/deltalake: Update SMBIOS type 4 -- Processor InformationMorgan Jang
TEST=Execute "dmidecode -t 4" to check if the processor information is correct for Deltalake platform Change-Id: I5d075bb297f2e71a2545ab6ad82304a825ed7d19 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30arch/x86/smbios.c: Split out weak functionsAngel Pons
The `smbios.c` file is rather long. To improve navigability, place weak function definitions on a separate compilation unit. Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30arch/x86/smbios.c: Factor out switch-case blockAngel Pons
Most of `smbios_fill_dimm_manufacturer_from_id()` is noise. Factor the switch into its own function to improve readability. Change-Id: Ia0757c01572709d16589a4ed622ca2d2cb69dda2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30arch/x86/smbios.c: Simplify assignmentAngel Pons
We can reduce the amount of duplicated code with a ternary operator. Change-Id: I8be95a62c54749d39e3e8821abd46d9f467a5a49 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30arch/x86/smbios.c: Clean up cosmeticsAngel Pons
Put `__weak` at the beginning of functions and reflow lines to leverage the increased line width of 96 characters. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I3a5fd2d4344b83e09f89053c083ec80aa297061e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30smbios: Fix type 17 for Windows 10Patrick Rudolph
The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows 10, returns an error if SMBIOS tables are invalid. Various tools use this API call and don't operate correctly if this fails. For example, the "Intel Processor Diagnostic Tool" program is affected. Windows then guesses the physical memory size by accumulating entries from the firmware-provided memory map, which results in a total memory size that is slightly lower than the actual installed memory capacity. To fix this issue, add the handle to a type 16 entry to all type 17 entries. Add new fields to struct memory_info and fill them in Intel common code. Use the introduced variables to fill type 16 in smbios.c and provide a handle to type 17 entries. Besides keeping the current behaviour on intel/soc/common platforms, the type 16 table is also emitted on platforms that don't explicitly fill it, by using the existing fields of struct memory_info. Tested on Windows 10: The GetPhysicallyInstalledSystemMemory API call doesn't return an error anymore and the installed memory is now being reported as 8192 MiB. Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-28arch/x86/smbios: Bump to version 3.0Patrick Rudolph
Fill in the new fields introduced with version 3.0 and install the new entry point structure identified by _SM3_. Tested on Linux 5.6 using tianocore as payload: Still able to decode the tables without errors. Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26arch/x86/smbios: Fix type4 for EDK2Patrick Rudolph
Mark the CPU as enabled and the socket as populated. EDK2 tests these flags before further reading this structure. Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26smbios: Add Type19Patrick Rudolph
Implement type 19 by accumulating the DRAM dimm size found in cbmem's CBMEM_ID_MEMINFO structure. This seems common on x86 where the address space always starts at 0. At least EDK2 uses this table in the UI and shows 0 MB DRAM if not present. Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-26arch/x86/smbios.c: Use macro for 'type_detail'Elyes HAOUAS
Change-Id: I95c40acb2fb390c50c8d1af9dd44999f9d57c2d5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04arch/x86/smbios: Add SMBIOS type8 dataBryantOu
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-28smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD ↵Johnny Lin
variable If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. VPD_SMBIOS_VERSION default is n. Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: insomniac <insomniac@slackware.it> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-06-25arch/x86/smbios: Add more fields to be overriden for type 3 and 4Johnny Lin
For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag() and add two functions that can override chassis version and serial_number. For type 4 add smbios_processor_serial_number() to override serial_number. Tested on OCP Tioga Pass. Change-Id: I80c6244580a4428fab781d760071c51c7933abee Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-09SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPEKyösti Mälkki
This gets rid of the magic numbers in Kconfig. Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06src/arch/x86: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-19src/arch: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32820 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26arch/x86: SMBIOS: Improve core count reportingAndrey Petrov
Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for "core count". However, it turns out this number has little to do with real number of cores. According to SDM vol 2A, it stays for "maximum number of addressable IDs for logical processors in this physical package". This does not seem to take into account fusing of giving processor. The new code determines 'core count' by dividing thread-level cpus by reported logical cores. This seems to be the only way to arrive to number of cores as it is reported in official CPU datasheet. TEST=tested on OCP monolake Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21cpu/amd/fam10: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13arch/x86: Correctly determine number of enabled coresAndrey Petrov
Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN which is correct. TEST=tested with dmidecode Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04smbios: Create a type for smbios_enclosure_typeMathew King
Add a name to the SMBIOS enclosure type enum and use it as the return type for smbios_mainboard_enclosure_type. BUG=b:143701965 TEST=compiles Change-Id: I816e17f0de2b0c119ddab638e57b0652f53f5b61 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36516 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28arch/x86: Populate more fields in SMBIOS type 4Andrey Petrov
If CPUID leaf 0x16 is available (Skylake and later) use it to obtain current and maximum speed. Otherwise call weak function that can be provided elsewhere (cpu/soc/mainboard). Also, populate "core enabled" with the same value as "core count". TEST=tested on OCP Monolake with dmidecode -t processor Change-Id: Ie5d88dacae6623dfa0ceb3ca1bb5eeff2adda103 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-10AUTHORS: Move src/arch/x86 copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-03smbios: Make SMBIOS type 3 enclosure type settable at runtimeMathew King
smbios.h had already declared smbios_mainboard_enclosure_type so this change defines it. It can be overridden in a mainboard so the enclosure type can be set at runtime. We have a mainboard that will be used in different enclosures and we are planning on using a single BIOS image for all of the enclosures so it will need to be set dynamically based on sku. BUG=b:138745917 TEST=Built arcada firmware and verified via dmidecode that enclosure type is correctly set to "Convertible", then temporarily added a smbios_mainboard_enclosure_type to arcadas board file returning 0x20 and verified with dmidecode that the enclosure type is "Detachable" Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-21arch: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h' Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21arch-x86/smbios: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
ALIGN_UP is an alias for ALIGN. Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33628 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19src/arch/x86/smbios: Change SMBIOS Version to 2.8Christian Walter
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were already pushed in https://review.coreboot.org/c/coreboot/+/33031 Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28src/arch/x86: Add automatic type41 entry creationChristian Walter
SMBIOS Type41 Entries will be automatically created. Type 41 entries define attributes of the onboard devices. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23src/mainboard/google: Adopt Mainboards to changed Type41 FuncChristian Walter
Required for automatic onboard device detection in the next patch. Change-Id: I3087de779faf8d006510c460b5372b22ae54b887 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-18SMBIOS: Fix SPD manufacture ID decoderLijian Zhao
According to JEP106 from JEDEC, fix manufacture ID of Crucial, Super Talnet and Micron. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I10a268a7f3bde405b95bd3a16d5d121be623c7ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/32837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07smbios: Walk over PCI devicetree to fill type 9Patrick Rudolph
Use the devicetree values for type 9 slots. Tested on Lenovo T520. Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23smbios: Add memory type 9 system slot supportLijian Zhao
Add SMBIOS type 9 system slots into coreboot, the definiation is up to date with SMBIOS spec 3.2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-19smbios: Fix copy paste errorPatrick Rudolph
As reported by Coverity Scan CID 1400679. Change-Id: I526b78a0697b7eb3c3dc75974c3a3a714b3d343f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32313 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19smbios: Add type 17 device/bank locator overrideLijian Zhao
Current SMBIOS type 17 device and bank locator string is like "Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or mainboard vendor a chance to replace with something matches with silkscreen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-09arch/x86/smbios: Reference type 7Patrick Rudolph
Fill in the handle to cache entries of type 7 in the type 4 structure. Tested on Intel Sandy Bridge (Lenovo T520). All 3 caches are referenced. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/smbios: Add type 7Patrick Rudolph
The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Tested on Intel Sandy Bridge (Lenovo T520). All 4 caches are displayed in dmidecode and show the correct information. Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-29arch/x86/smbios(type4): Write processor_upgrade fieldElyes HAOUAS
Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29529 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27Revert "src/arch: An upgrade of SMBIOS to latest version 3.2"Nico Huber
This reverts commit b7daf7e8fa18de7bfb3cd102791bc6af89bac4b6. The review was spread across four different change-ids. Of course, not all comments were addressed, now coverity complains too. Change-Id: If5dbc1ae37120330ab192fb15eb4984afc84a7af Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22src/arch: An upgrade of SMBIOS to latest version 3.2Francois Toguo
This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: Iab98e063874c9738e48a387cd91341d266391156 Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-23arch/x86/smbios.c: Remove duplicated 'processor_upgrade'Elyes HAOUAS
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15SMBIOS: Update BIOS Information (Type 0) to version V3.2.0Elyes HAOUAS
Add Extended BIOS ROM Size field. Change-Id: Iec35c8c66210f0ddc07a2ca6f976a1f8fc53037d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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