coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2012-07-03	Fix the error message for romstage when .bss or .data are non-zero	Ronald G. Minnich
2012-05-15	Change the name of the romstage bootblock.ld	Marc Jones
2012-04-06	Fix support for RAM-less multi-processor init	Kyösti Mälkki
2012-03-31	Add support for RAM-less multi-processor init	Kyösti Mälkki
2012-03-29	Add infrastructure for global data in the CAR phase of boot	Gabe Black
2012-03-25	Makefile: rename linker intermediate variable	Kyösti Mälkki
2012-03-17	Another indirection for normal/fallback bootblock	Patrick Georgi
2012-03-16	Rename AMD_AGESA to CPU_AMD_AGESA	Kyösti Mälkki
2011-12-24	Only BSP CPU writes CMOS in bootblock code	Kyösti Mälkki
2011-12-08	Fix ldscript for bootblock .rom section	Kyösti Mälkki
2011-11-24	Remove unused code files and cosmetic changes	Kyösti Mälkki
2011-11-22	Fix post_code in 16bit entry	Kyösti Mälkki
2011-10-19	Drop eh_frame instead of moving it into the image.	Stefan Reinauer
2011-10-14	Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6	Stefan Reinauer
2011-04-19	Recently the 3 projects using the new AMD reference code have been	Scott Duplichan
2011-04-16	bootblock updates: ...	Stefan Reinauer
2011-04-15	comment cosmetics in bootblock.ld	Stefan Reinauer
2011-04-14	- drop remaining CONFIG_ROM_IMAGE_SIZE	Stefan Reinauer
2011-04-11	Unify use of post_code	Alexandru Gagniuc
2011-03-08	Move cmos.default handling to bootblock	Patrick Georgi
2011-02-14	This code fixes a number of build issues related to the AMD Agesa code. The p...	Frank Vibrans
2010-12-11	After this has been brought up many times before, rename src/arch/i386 to	Stefan Reinauer