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2013-03-07Remove UTF-8 characters from commentsRonald G. Minnich
I've used an operating system for over 10 years now that makes UTF-8 easy. It's not called Linux or OSX. When UTF-8 is needed, of course, then we can look again. I can't think of a single redeeming feature of placing it in the comment in this manner. It's certainy not needed. The inclusion of UTF-8 characters is inconvenient, especially from a text terminal. I don't really want to start using compose in CROSH shell terminals on chromeos. We might want to incorporate "no UTF-8" as a commit filter. For now, get rid of these characters. Change-Id: If94cc657bae1dbd282bec8de6c5309b1f8da5659 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2604 Reviewed-by: Bernhard Urban <lewurm@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07src/arch/x86/boot/acpigen.c: Small coding style and comment fixesPaul Menzel
While reading through the file fix some spotted errors like indentation, locution(?), capitalization and missing full stops. Change-Id: Id435b4750e329b06a9b36c1df2c39d2038a09b18 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2484 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-28Drop CONFIG_WRITE_HIGH_TABLESStefan Reinauer
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-04smbios: show CONFIG_LOCALVERSION in DMI bios_versionChristian Gmeiner
If somebody makes use of CONFIG_LOCALVERSION show this user provided config string for DMI bios_version. As requested I have attached example output. CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version 4.0-3360-g5be6673-dirty CONFIG_LOCALVERSION="V1.01.02 Beta" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y ... root@OT:~# cat /sys/class/dmi/id/bios_version V1.01.02 Beta Change-Id: I5640b72b56887ddf85113efa9ff23df9d4c7eb86 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/2279 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30Extend CBFS to support arbitrary ROM source media.Hung-Te Lin
Summary: Isolate CBFS underlying I/O to board/arch-specific implementations as "media stream", to allow loading and booting romstage on non-x86. CBFS functions now all take a new "media source" parameter; use CBFS_DEFAULT_MEDIA if you simply want to load from main firmware. API Changes: cbfs_find => cbfs_get_file. cbfs_find_file => cbfs_get_file_content. cbfs_get_file => cbfs_get_file_content with correct type. CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM, the ROM may come from USB, UART, or SPI -- any serial devices and not available for memory mapping. To support these devices (and allowing CBFS to read from multiple source at the same time), CBFS operations are now virtual-ized into "cbfs_media". To simplify porting existing code, every media source must support both "reading into pre-allocated memory (read)" and "read and return an allocated buffer (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*" provides simple memory mapping simulation. Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA is defined for CBFS functions to automatically initialize a per-board default media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS function names relying on memory mapped backend (ex, "cbfs_find" => actually loads files). Now we only have two getters: struct cbfs_file *entry = cbfs_get_file(media, name); void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type); Test results: - Verified to work on x86/qemu. - Compiles on ARM, and follow up commit will provide working SPI driver. Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12Implement GCC code coverage analysisStefan Reinauer
In order to provide some insight on what code is executed during coreboot's run time and how well our test scenarios work, this adds code coverage support to coreboot's ram stage. This should be easily adaptable for payloads, and maybe even romstage. See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for more information. To instrument coreboot, select CONFIG_COVERAGE ("Code coverage support") in Kconfig, and recompile coreboot. coreboot will then store its code coverage information into CBMEM, if possible. Then, run "cbmem -CV" as root on the target system running the instrumented coreboot binary. This will create a whole bunch of .gcda files that contain coverage information. Tar them up, copy them to your build system machine, and untar them. Then you can use your favorite coverage utility (gcov, lcov, ...) to visualize code coverage. For a sneak peak of what will expect you, please take a look at http://www.coreboot.org/~stepan/coreboot-coverage/ Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2052 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11cbmem: replace pointer type by uint64_tStefan Reinauer
Since coreboot is compiled into 32bit code, and userspace might be 32 or 64bit, putting a pointer into the coreboot table is not viable. Instead, use a uint64_t, which is always big enough for a pointer, even if we decide to move to a 64bit coreboot at some point. Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2135 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-15Fix a compare against undefined variable in acpi.cMartin Roth
Initialize the pointer fadt to NULL to prevent a later comparison (if (fadt == NULL)) when the pointer had the *possibility* of never having been initialized. Change-Id: Ib2a544c190b609ab8c23147dc69dca5f4ac7f38c Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2037 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-12-06Unify assembler function handlingStefan Reinauer
Instead of adding regparm(0) to each assembler function called by coreboot, add an asmlinkage macro (like the Linux kernel does) that can be different per architecture (and that is empty on ARM right now) Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1973 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-29pirq_route_irqs is privatePatrick Georgi
Change-Id: I120913dac3150a72c2e66c74872ee00074ee0267 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Restore GNVS pointer in the resume pathDuncan Laurie
The SMM GNVS pointer is normally updated only when the ACPI tables are created, which does not happen in the resume path. In order to restore this pointer it needs to be available at resume time. The method used to locate it at creation time cannot be used again as that magic signature is overwritten with the address itself. So a new CBMEM ID is added to store the 32bit address so it can be found again easily. A new function is defined to save this pointer in CBMEM which needs to be called when the ACPI tables are created in each mainboard when write_acpi_tables() is called. The cpu_index variable had to be renamed due to a conflict when cpu/cpu.h is added for the smm_setup_structures() prototype. Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12oprom: Ensure that mode information is valid before putting it in the tables.Gabe Black
At least when CONFIG_CHROMEOS is turned on, it's possible for CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid information to put into the framebuffer coreboot table. That means that what's put in there is junk, probably all zeroes from the uninitialized global variable the mode information is stored in (mode_info). When a payload uses libpayload and turns on the coreboot framebuffer console, that console will attempt to scroll at some point and decrease the cursor's y coordinate until it is less than the number of rows claimed by the console. The number of rows is computed by taking the vertical resolution of the framebuffer and dividing it by the height of the font. Because the mode information was all zeroes, the coreboot table info is all zeroes, and that means that the number of rows the console claims is zero. You can't get the unsigned y coordinate of the cursor to be less than zero, so libpayload gets stuck in an infinite loop. The solution this change implements is to add a new function, vbe_mode_info_valid, which simply returns whether or not mode_info has anything in it. If not, the framebuffer coreboot table is not created, and libpayload doesn't get stuck. Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Define post codes for OS boot and resumeDuncan Laurie
And move the pre-hardwaremain post code to 0x79 so it comes before hardwaremain at 0x80. Emit these codes from ACPI OS resume vector as well as the finalize step in bd82x6x southbridge. Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06acpi: Add support for DMAR tables (Intel IOMMU support)Patrick Georgi
Adds lowlevel handling of DMAR tables for use by mainboards' ACPI code. Not much automagic (yet). Change-Id: Ia86e950dfcc5b9994202ec0e2f6d9a2912c74ad8 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-10-27Take care of NULL chip_ops->nameKyösti Mälkki
Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-07Take care of NULL chip_ops->nameKyösti Mälkki
Change-Id: I62b1c497d23ec2241efb963e7834728085824016 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1565 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-10-04pirq_routing: Allow routing with more than 4 PIRQ linksAlexandru Gagniuc
pirq_routing_irqs assumed that only four links are available for PIRQ routing, INTA to INTD. Some chipsets provide more, up to INTH. When pirq_routing_irqs found a link number greater than 4 in the pirq table, it would not assign that IRQ. This is a shame, as it limits the flexibility of routing IRQs. Make the maximum number of links a Kconfig variable, and modify the code to respect it. This works beatifully on the VX900, which provides 8 routable interrupts. While we're at it, also refactor pirq_routing_irqs, and add some much needed comments. Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this function. The copyrights added were determined from git log filename. Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1482 Tested-by: build bot (Jenkins)
2012-08-25MPTABLE: check for fixed IRQ entries on all pinsSven Schnelle
Don't derive the IRQ pin from the function number. Especially onboard chipset devices don't follow that rule. Instead check and add all fixed IRQ entries. Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1461 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22mptable: bring sanity back to mptable generation (TRIVIAL)Alexandru Gagniuc
Remove extra semicolon Capitalize beginning of printk sentence Fix detection of multiple ISA-carrying IOAPICs Fix whitespace issue Change-Id: I114119b1daf3b472955c0dd00bdc449401789525 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1474 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-21Don't write automatic IRQ entries for disabled devicesSven Schnelle
Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1460 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-08Do not allow modifying memory table directlyKyösti Mälkki
Adding ranges directly into coreboot memory table raised issues as those methods bypassed the MTRR setup. Such regions are now added as resources, so declare the functions again as static. Change-Id: If78613da40eabc5c99c49dbe2d6047cb22a71b69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1415 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-08Drop HAVE_MAINBOARD_RESOURCESKyösti Mälkki
These existed to provide a hook to add reserved memory regions in the coreboot memory table. Reserved memory are now added as resources. Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
The existing NVS variable for PPCM will be used to select a dynamic max P-state. By itself this does not change existing behavior because the NVS PPCM variable is initialized to zero. PPCM can be tested by building and booting a modified BIOS that sets gnvs->ppcm to a value greater than 1 and checking from the OS that the P-state is limited to that value. Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25Extend smbios api to allow runtime change of mainboard serial and versionChristian Gmeiner
This patch extends the current smbios api to allow changing mainboard serial and version during coreboot runtime. This is helpful if you have an EEPROM etc. to access these informations and want to add some quirks for broken hardware revision for the linux kernel. This could be done via DMI_MATCH marco. Change-Id: I1924a56073084e965a23e47873d9f8542070423c Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1232 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-25ELOG: Add support for generating SMBIOS type15 tableDuncan Laurie
This standared SMBIOS 0able describes the location and format of the event log to the OS and applications. In this case the pointer is a 32bit physical address pointer to the log in memory mapped flash. Look for SMBIOS type15 entry with 'dmidecode -t 15' Handle 0x0004, DMI type 15, 23 bytes System Event Log Area Length: 4095 bytes Header Start Offset: 0x0000 Header Length: 8 bytes Data Start Offset: 0x0008 Access Method: Memory-mapped physical 32-bit address Access Address: 0xFFB6F000 Status: Valid, Not Full Change Token: 0x00000000 Header Format: OEM-specific Supported Log Type Descriptors: 0 Change-Id: I1e7729e604000f197e26e69991a2867e869197a6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1314 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-13MPTAPLE: generate from devicetree.cbSven Schnelle
This patch adds support for autogenerating the MPTABLE from devicetree.cb. This is done by a write_smp_table() declared weak in mpspec.c. If the mainboard doesn't provide it's own function, this generic implementation is called. Syntax in devicetree.cb: ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN> The ioapic_irq directive can be used in pci and pci_domain devices. If there's no directive, the autogen code traverses the tree back to the pci_domain and stops at the first device which such a directive, and use that information to generate the entry according to PCI IRQ routing rules. Change-Id: I4df5b198e8430f939d477c14c798414e398a2027 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1138 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03SMBIOS: move serial number and version out to KconfChristian Gmeiner
With this change it is possible to define serial number and version of the mainboard. These informations are used in SMBIOS tables. Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1163 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-30Initializer of a static member in union.zbao
It is just me or does anybody have the same build error without this patch? ------ src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC': src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv' specified in initializer src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around initializer src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization for 'addr.<anonymous>') ------- Anyway, I believe at least this will cause warnings. "resv" is a member of a union, not of acpi_addr_t. So it should be wrapped by a brace in the initializer. Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-03Print some useful debugging information in PSS table creationStefan Reinauer
Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd Example: PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 PSS: 1900MHz power 35000 control 0x1300 status 0x1300 PSS: 1600MHz power 28468 control 0x1000 status 0x1000 PSS: 1400MHz power 24291 control 0xe00 status 0xe00 PSS: 1200MHz power 20340 control 0xc00 status 0xc00 PSS: 1000MHz power 16569 control 0xa00 status 0xa00 PSS: 800MHz power 12937 control 0x800 status 0x800 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/994 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-03Make creation of CBMEM_ID_RESUME_SCRATCH depending on AgesaStefan Reinauer
The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one particular board (AMD Persimmon). Make the creation of that section depending on Agesa so it does consume space on non-Agesa systems. Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/992 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30acpigen: make acpigen_write_CST_package_entry non-staticStefan Reinauer
It's used by Sandybridge specific C state generation code. Change-Id: Ia6f1e14e748841a9646fd93d0a18f9e8f2a55e29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/949 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30acpigen: Add support for generating T state tablesStefan Reinauer
Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/944 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-30Rework ACPI CST table generationStefan Reinauer
... in order to unify the Sandybridge and Lenovo implementations currently used in the tree. - use acpi_addr_t in acpigen_write_register() - use acpi_cstate_t for cstate tables (and fix up the x60 and t60) - drop cst_entry from acpigen.h Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/943 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-28acpigen: make acpigen_write_len_f() non staticStefan Reinauer
since it is used in CPU specific ACPI generation code Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/947 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-27coreboot_table.c: Add missing include filesStefan Reinauer
If compiling coreboot with ChromeOS support, two more include files are required. Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/931 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-16S3 code in coreboot public folder.zbao
1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16ACPI HEST table.zbao
HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/888 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-05smbios: Don't fill out firmware version on ChromeOSStefan Reinauer
In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/867 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Fill out ChromeOS specific coreboot table extensionsStefan Reinauer
ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/866 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support for mainboard specific suspend/resume handlerStefan Reinauer
Some mainboards (most likely laptops) will need mainboard specific functions called upon a resume from suspend. Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Drop verified boot code from acpi.cStefan Reinauer
We changed our verified boot initialization to run from romstage, as that allows faster boot times and does not add as much ChromeOS specific code to generic files. Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30use movsl for copying resume memory backStefan Reinauer
It's not significantly faster, but easier to read and smaller. Change-Id: Ibab0b478873912d67bf1f07743f628586353368a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/755 Reviewed-by: Mathias Krause <minipli@googlemail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30Add timestamps for selfboot and acpi wakeDuncan Laurie
Change-Id: I28224867610b947739d940d25c98399d219f10f4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30Add TPM support to corebootStefan Reinauer
and initialize the TPM on S3 resume This patch integrates the TPM driver and runs TPM resume upon an ACPI S3 resume without including any other parts of vboot. We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS (that are incompatible with coreboot's) and it does a lot more than we want it to do. Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-29Refactor publishing CBMEM addresses through coreboot table.Vadim Bendebury
We need to provide u-boot access to several different CBMEM sections. To do that, a common coreboot table structure is used, just different tags match different coreboot table sections. Also, the code is added to export CBMEM console and MRC cache addresses through the same mechanism. Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/724 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29Add timestamp table pointer to the coreboot table.Vadim Bendebury
This change exports the timestamp table pointer through coreboot table to make it possible for u-boot to add timestamps to the table. Inclusion of cbmem.h allows to drop external declarations in coreboot_table.c. Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/716 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-20Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 ↵Rudolf Marek
class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/683 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-10If the memory mapped UART isn't present, leave it out of the cb tables.Gabe Black
This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/729 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-03-09Increase size of the coreboot table areaStefan Reinauer
Packing a device tree into the coreboot table can easily make the table exceed the current limit of 8KB. However, right now there is no error handling in place to catch that case. Increase the maximum memory usable for all tables from 64KB to 128KB and increase the maximum coreboot table size from 8KB to 32KB. Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/704 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix compilation when USE_OPTION_TABLE is not defined.Duncan Laurie
Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/702 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Fix coreboot table size calculations.Vadim Bendebury
The code when reporting the coreboot table size did not account for the last added table record. This change fixes the problem. . rebuild coreboot, program it on the target, restart it . look for 'Wrote coreboot table at:' in the console log . observe the adequate table size reported $ grep 'Wrote coreboot table:' /tmp/cb.log Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45 $ Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/703 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09Clean up use of CONFIG_ variables in coreboot_table.cStefan Reinauer
CONFIG_ variables are used inconsistently within the file src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong thing if the option is disabled. #if (CONFIG_FOO == 1) is not needed. Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/701 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-03-08Unify Local APIC address definitionsPatrick Georgi
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Move linux 2.6.11 workaround to generic codePatrick Georgi
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25ACPI: Add function for writing _CST tablesSven Schnelle
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/312 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-13Prevent build breakage without consoles enabledStefan Reinauer
If all console types are disabled, coreboot will fail to compile because static code is unused. This patch fixes the issue. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2 Reviewed-on: http://review.coreboot.org/260 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13refactor vesa mode setting code and bootsplash codeStefan Reinauer
- adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/256 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-07-02whitespace-only changes in acpi.c, replaced spaces with tabsCristian Măgherușan-Stanciu
Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/74 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14fix coreboot compilation without serial console enabled.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-24This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.Josef Kellermann
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21... And fix the other compile time issues in cmos_layout.bin supportPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18Report if cmos_layout.bin can't be found when it should.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18Move option table (cmos.layout's binary representation)Patrick Georgi
to CBFS and adapt coreboot to use it. Comments by Stefan and Mathias taken into account (except for the build time failure if the table is missing when it should exist and the "memory leak" in build_opt_tbl) Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16Get mptable OEM/product ID from kconfig variables.Uwe Hermann
We currently use "COREBOOT" unconditionally as the "OEM ID" in our mptable.c files, and hardcode the mainboard name in mptable.c like this: mptable_init(mc, "DK8-HTX ", LAPIC_ADDR); However, the spec says "OEM ID: A string that identifies the manufacturer of the system hardware." (Table 4-2, page 42) so "COREBOOT" doesn't match the spec, we should use the hardware vendor name. Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID" (truncate/fill it to 8 characters as per spec). Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID", and truncate/fill it to 12 characters as per spec, if needed. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11After this has been brought up many times before, rename src/arch/i386 toStefan Reinauer
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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