coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-01-17	riscv: create Kconfig architecture features for new parts	Ronald G. Minnich
2019-01-16	buildsystem: Promote rules.h to default include	Kyösti Mälkki
2018-12-19	arch/riscv: Don't set FPU state to "dirty"	Jonathan Neuschäfer
2018-12-19	arch/riscv: Define and use SBI_ENOSYS	Jonathan Neuschäfer
2018-12-18	arch/riscv: Don't hardcode CSR numbers anymore	Jonathan Neuschäfer
2018-12-07	riscv: fix non-SMP support	Philipp Hug
2018-11-19	src: Add required space after "switch"	Elyes HAOUAS
2018-11-05	riscv: add support for supervisor binary interface (SBI)	Xiang Wang
2018-11-05	riscv: add support to block smp in each stage	Xiang Wang
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-30	riscv: simplify timer interrupt handling	Philipp Hug
2018-10-30	src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode	Philipp Hug
2018-10-11	selfboot: remove bounce buffers	Ronald G. Minnich
2018-10-11	riscv: add physical memory protection (PMP) support	Xiang Wang
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-10-06	arch/riscv: Update comment about mstatus initialization	Jonathan Neuschäfer
2018-10-04	arch/riscv: Adjust compiler flags for scan-build	Jonathan Neuschäfer
2018-09-26	arch/riscv: Advance the PC after handling misaligned load/store	Jonathan Neuschäfer
2018-09-21	arch/riscv/include/arch: Don't use device_t	Elyes HAOUAS
2018-09-16	riscv: don't write to mstatus.XS	Xiang Wang
2018-09-15	arch/riscv: Configure delegation only if S-mode is supported	Jonathan Neuschäfer
2018-09-14	arch/riscv: Only execute on hart 0 for now	Philipp Hug
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	arch/riscv: add missing endian.h header to io.h	Philipp Hug
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-10	riscv: update misaligned memory access exception handling	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-05	riscv: add entry assembly file for RAMSTAGE	Xiang Wang
2018-09-05	riscv: add support to check machine length at runtime	Xiang Wang
2018-09-04	riscv: add spin lock support	Xiang Wang
2018-09-04	riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page	Xiang Wang
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-08-30	riscv: update the definition of intptr_t/uintptr_t	Xiang Wang
2018-08-07	arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)	Julius Werner
2018-08-01	riscv: remove redundancy in Makefile	Xiang Wang
2018-07-31	riscv: fix issues (timestrap & PRIu64)	Xiang Wang
2018-07-30	riscv: delete src/arch/riscv/prologue.inc	Xiang Wang
2018-07-18	arch/riscv: Fix makefile to only set flags for riscv	Martin Roth
2018-07-18	riscv: add CAR interface	Xiang Wang
2018-07-17	riscv: add support for modifying compiler options	Xiang Wang
2018-07-12	riscv: add include/arch/smp/ directory	Xiang Wang
2018-07-11	riscv: add support to check ISA extension	Xiang Wang
2018-07-06	riscv: use __riscv_atomic to check support A extension	Xiang Wang
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
2018-04-26	arch/riscv: Store mprv bit in size_t	Jonathan Neuschäfer
2018-04-11	arch/riscv: Remove I/O space access functions (outb, etc.)	Jonathan Neuschäfer
2018-02-20	arch/riscv: Delegate the page fault exceptions	Jonathan Neuschäfer
2018-02-20	arch/riscv: Update encoding.h and adjust related code	Jonathan Neuschäfer
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2018-02-20	arch/riscv: Don't set up virtual memory	Jonathan Neuschäfer
2018-02-20	arch/riscv: Make RVC support configurable	Jonathan Neuschäfer
2018-02-20	arch/riscv: Align trap_entry to 4 bytes, as required by spec	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove supervisor_trap_entry	Jonathan Neuschäfer
2017-12-02	riscv: Remove config string support	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer
2017-12-02	arch/riscv: Return from trap_handler instead of jumping out	Jonathan Neuschäfer
2017-12-02	arch/riscv: Unify trap return	Jonathan Neuschäfer
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-11-07	arch/riscv: Use a separate trap stack	Jonathan Neuschäfer
2017-11-07	arch/riscv: gettimer: Don't use the config string	Jonathan Neuschäfer
2017-11-07	arch/riscv: Drop mret workaround	Jonathan Neuschäfer
2017-11-07	arch/riscv: mprv_read_*: Mark result as earlyclobber	Jonathan Neuschäfer
2017-11-07	arch/riscv: Fix return type of mprv_read_u64	Jonathan Neuschäfer
2017-09-27	arch/riscv: hls_init: Initialize time{,cmp} with dummy pointers	Jonathan Neuschäfer
2017-09-27	arch/riscv: Document mprv_{read,write}_* functions	Jonathan Neuschäfer
2017-09-27	arch/riscv: trap handler: Print load/store access width in bits	Jonathan Neuschäfer
2017-09-26	riscv: Update register address	wxjstz
2017-07-25	src/arch: Fix checkpatch warning: no spaces at the start of a line	Martin Roth
2017-07-07	arch/*: Update Kconfig symbol usage	Martin Roth
2017-06-07	src: change coreboot to lowercase	Martin Roth
2017-05-30	arch: Unify basic cache clearing API	Julius Werner
2017-02-20	riscv: Suppress invalid coverity errors	Martin Roth
2017-01-16	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-12-20	riscv: enable counters via m[us]counteren	Ronald G. Minnich
2016-12-18	riscv: Add support for timer interrupts	Ronald G. Minnich
2016-12-06	riscv: Stub out sbi_(un)mask_interrupt	Jonathan Neuschäfer
2016-12-06	arch/riscv/mcall.c: Return the correct memory base and size	Jonathan Neuschäfer
2016-11-20	riscv: map first 4GiB of physical address space	Ronald G. Minnich
2016-11-14	riscv: add a variable to control trap management	Ronald G. Minnich
2016-11-13	riscv: change payload() to pass the config string pointer as arg0	Ronald G. Minnich
2016-11-12	riscv: start to use the configstring functions	Ronald G. Minnich
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-18	arch/riscv: In trap handler, don't print SP twice	Jonathan Neuschäfer
2016-10-15	arch/riscv: Visually align trap frame information	Jonathan Neuschäfer
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
2016-10-15	arch/riscv: Remove unused bootblock_simple.c	Jonathan Neuschäfer
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-15	riscv and power8: Convert printk/while(1) to die	Jonathan Neuschäfer
2016-10-07	RISCV: update the encoding.h file.	Ronald G. Minnich
2016-09-12	src/arch: Improve code formatting	Elyes HAOUAS
2016-08-29	arch/riscv: Add missing "break;"	Jonathan Neuschäfer
2016-08-23	arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode	Jonathan Neuschäfer
2016-08-23	arch/riscv: Map the kernel space into RAM (2GiB+)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Enable U-mode/S-mode counters (stime, etc.)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Fix unaligned memory access emulation	Jonathan Neuschäfer