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path: root/src/arch/riscv/trap_handler.c
AgeCommit message (Expand)Author
2023-12-20arch/riscv: Use same indent levels for switch/caseFelix Singer
2023-04-21arch/riscv/trap_handler.c: Use new names for CSRArthur Heymans
2022-11-22src/arch: Remove unnecessary space after castsElyes Haouas
2021-09-17arch/riscv/trap_handler: add missing types.h includeFelix Held
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-03-06src/arch/riscv: Convert to SPDX license headerPatrick Georgi
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-02-02riscv: Show hart id in trap handlerPhilipp Hug
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-05riscv: add support for supervisor binary interface (SBI)Xiang Wang
2018-10-30riscv: simplify timer interrupt handlingPhilipp Hug
2018-09-10riscv: update misaligned memory access exception handlingXiang Wang
2018-02-20arch/riscv: Update encoding.h and adjust related codeJonathan Neuschäfer
2017-12-02riscv: Remove config string supportJonathan Neuschäfer
2017-12-02arch/riscv: Remove the current SBI implementationJonathan Neuschäfer
2017-12-02arch/riscv: Return from trap_handler instead of jumping outJonathan Neuschäfer
2017-12-02arch/riscv: Unify trap returnJonathan Neuschäfer
2017-11-07arch/riscv: gettimer: Don't use the config stringJonathan Neuschäfer
2017-09-27arch/riscv: trap handler: Print load/store access width in bitsJonathan Neuschäfer
2017-06-07src: change coreboot to lowercaseMartin Roth
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
2017-01-16riscv: get SBI calls to workRonald G. Minnich
2016-12-18riscv: Add support for timer interruptsRonald G. Minnich
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
2016-11-02riscv: Add a bandaid for the new toolchainRonald G. Minnich
2016-10-18arch/riscv: In trap handler, don't print SP twiceJonathan Neuschäfer
2016-10-15arch/riscv: Visually align trap frame informationJonathan Neuschäfer
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
2016-08-29arch/riscv: Add missing "break;"Jonathan Neuschäfer
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
2016-08-15arch/riscv: Improve and refactor trap handling diagnosticsJonathan Neuschäfer
2016-07-19arch/riscv: Enable unaligned load handlingJonathan Neuschäfer
2016-06-28arch/riscv: Show fault PC and load address on load access faultsJonathan Neuschäfer
2016-02-19RISC-V: Add more debug info to debug printksAndrew Waterman
2016-02-19RISC-V: Make inline asm usage saferAndrew Waterman
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-09-15riscv-trap-handling: Add functionality, prevent stack corruptionThaminda Edirisooriya
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya