| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-06 | src/arch/riscv: Convert to SPDX license header | Patrick Georgi |
| 2019-08-03 | riscv: add support for OpenSBI | Xiang Wang |
| 2019-06-23 | riscv: use mret to invoke M-mode payload and disable interrupts | Xiang Wang |
| 2019-02-09 | riscv: Use correct argument in a1 when invoking payload | Philipp Hug |
| 2019-02-02 | riscv: Simplify payload handling | Xiang Wang |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |