coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-06-23	riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths	Xiang Wang
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Separate MMIO and PNP ops	Kyösti Mälkki
2019-02-13	riscv: Add initial support for 32bit boards	Philipp Hug
2019-02-02	riscv: Simplify payload handling	Xiang Wang
2018-12-19	arch/riscv: Define and use SBI_ENOSYS	Jonathan Neuschäfer
2018-11-05	riscv: add support for supervisor binary interface (SBI)	Xiang Wang
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-11	riscv: add physical memory protection (PMP) support	Xiang Wang
2018-10-08	Move compiler.h to commonlib	Nico Huber
2018-09-21	arch/riscv/include/arch: Don't use device_t	Elyes HAOUAS
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	arch/riscv: add missing endian.h header to io.h	Philipp Hug
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-10	riscv: update misaligned memory access exception handling	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-05	riscv: add entry assembly file for RAMSTAGE	Xiang Wang
2018-09-05	riscv: add support to check machine length at runtime	Xiang Wang
2018-09-04	riscv: add spin lock support	Xiang Wang
2018-09-04	riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page	Xiang Wang
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-08-30	riscv: update the definition of intptr_t/uintptr_t	Xiang Wang
2018-08-07	arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)	Julius Werner
2018-07-31	riscv: fix issues (timestrap & PRIu64)	Xiang Wang
2018-07-12	riscv: add include/arch/smp/ directory	Xiang Wang
2018-07-11	riscv: add support to check ISA extension	Xiang Wang
2018-07-06	riscv: use __riscv_atomic to check support A extension	Xiang Wang
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
2018-04-26	arch/riscv: Store mprv bit in size_t	Jonathan Neuschäfer
2018-04-11	arch/riscv: Remove I/O space access functions (outb, etc.)	Jonathan Neuschäfer
2018-02-20	arch/riscv: Update encoding.h and adjust related code	Jonathan Neuschäfer
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2018-02-20	arch/riscv: Don't set up virtual memory	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove the current SBI implementation	Jonathan Neuschäfer
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-11-07	arch/riscv: mprv_read_*: Mark result as earlyclobber	Jonathan Neuschäfer
2017-11-07	arch/riscv: Fix return type of mprv_read_u64	Jonathan Neuschäfer
2017-09-27	arch/riscv: Document mprv_{read,write}_* functions	Jonathan Neuschäfer
2017-07-25	src/arch: Fix checkpatch warning: no spaces at the start of a line	Martin Roth
2017-07-07	arch/*: Update Kconfig symbol usage	Martin Roth
2017-05-30	arch: Unify basic cache clearing API	Julius Werner
2017-02-20	riscv: Suppress invalid coverity errors	Martin Roth
2017-01-16	riscv: Move mcall numbers to mcall.h, adjust their names	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-12-18	riscv: Add support for timer interrupts	Ronald G. Minnich
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-07	RISCV: update the encoding.h file.	Ronald G. Minnich
2016-09-12	src/arch: Improve code formatting	Elyes HAOUAS
2016-08-23	arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Print the page table structure after construction	Jonathan Neuschäfer
2016-08-11	arch/riscv: Update encoding.h and dependent files	Jonathan Neuschäfer
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-28	arch/riscv: Remove spinlock code from atomic.h	Jonathan Neuschäfer
2016-07-19	arch/riscv: Enable unaligned load handling	Jonathan Neuschäfer
2016-07-18	arch/riscv: Remove enter_supervisor	Jonathan Neuschäfer
2016-06-12	arch/riscv: copy read/write8/16/32 from x86	Jonathan Neuschäfer
2016-05-02	lib/coreboot_table: use the architecture dependent table size	Aaron Durbin
2016-05-02	arch: introduce architecture dependent common variables	Aaron Durbin
2016-02-11	arches: lib: add main_decl.h for main() declaration	Aaron Durbin
2016-02-11	arch/{arm64,riscv}: remove jmp_to_elf_entry() declaration	Aaron Durbin
2016-02-11	arch: remove stage_exit()	Aaron Durbin
2016-01-18	arch/riscv: Add missing license headers	Martin Roth
2015-11-11	arm/arm64: Generalize bootblock C entry point	Julius Werner
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya
2015-09-15	riscv-trap-handling: Add functionality, prevent stack corruption	Thaminda Edirisooriya
2015-09-10	riscv-trap-handling: Add implementation for trap calls in riscv	Thaminda Edirisooriya
2015-09-10	riscv-virtual-memory: Add virtual memory setup	Thaminda Edirisooriya
2015-08-26	riscv-trap-handling: Add preliminary trap handling for riscv	Thaminda Edirisooriya
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-21	Unify byte order macros and clrsetbits	Julius Werner
2015-04-06	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner
2015-02-02	src/arch/*/include/stdint.h: Provide definitions for bool type	Alexandru Gagniuc
2015-01-27	CBMEM: Tidy up CAR migration	Kyösti Mälkki
2015-01-27	CBMEM console: Fix CAR migration step	Kyösti Mälkki
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich