coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-01-18	arch/riscv: Add missing license headers	Martin Roth
2015-11-11	arm/arm64: Generalize bootblock C entry point	Julius Werner
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya
2015-09-15	riscv-trap-handling: Add functionality, prevent stack corruption	Thaminda Edirisooriya
2015-09-10	riscv-trap-handling: Add implementation for trap calls in riscv	Thaminda Edirisooriya
2015-09-10	riscv-virtual-memory: Add virtual memory setup	Thaminda Edirisooriya
2015-08-26	riscv-trap-handling: Add preliminary trap handling for riscv	Thaminda Edirisooriya
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-21	Unify byte order macros and clrsetbits	Julius Werner
2015-04-06	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner
2015-02-02	src/arch/*/include/stdint.h: Provide definitions for bool type	Alexandru Gagniuc
2015-01-27	CBMEM: Tidy up CAR migration	Kyösti Mälkki
2015-01-27	CBMEM console: Fix CAR migration step	Kyösti Mälkki
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich