coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-09-14	arch/riscv: Only execute on hart 0 for now	Philipp Hug
2018-07-18	riscv: add CAR interface	Xiang Wang
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-07-28	arch/riscv: Refactor bootblock.S	Jonathan Neuschäfer
2016-06-28	riscv/bootblock.S: Register machine-mode, not supervisor-mode trap handler	Jonathan Neuschäfer
2016-06-28	arch/riscv: Move _start to the beginning of the bootblock	Jonathan Neuschäfer
2016-06-21	riscv-spike: Move coreboot to 0x80000000 (2GiB)	Jonathan Neuschäfer
2016-04-08	Change la to li (load immediate)	Ronald G. Minnich
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-18	riscv: use new-style CBFS header lookup	Patrick Georgi
2015-04-06	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich