| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-02-11 | src/arch/ppc64/*: pass FDT address to payload | Sergii Dmytruk | |
| It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> | |||
| 2022-02-11 | ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment | Krystian Hebel | |
| BSS is loaded as part of the bootblock, it is zeroed in the file so it doesn't have to be cleared explicitly by the code. Code for clearing is left as a comment along with a warning about alignment requirements. Vector operations are sometimes generated for code such as 'uint8_t x[32] = {0}', this results in an exception when vector registers (VR) are not enabled. VSR (vector-scalar register) operations are also enabled, there is no reason not to. Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> | |||
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