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path: root/src/arch/arm64/include/armv8
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2015-03-28arm64: remove EL and mode from secmon_paramsAaron Durbin
Since PSCI dynamically determines which EL to transition to based on SCR_EL3 there's no need to provide that information. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel with MP. Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: split cpu.cAaron Durbin
The cpu.c contains some helpful construts as well as ramstage devicetree handling. Split the 2 pieces so that cpu.c can be reused in secmon. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted. Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218842 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9089 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: exception handler registrationAaron Durbin
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add cpu_is_bsp() conceptAaron Durbin
It's helpful to know if the current running CPU is the BSP. Therefore, provide that semantic. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172 Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218653 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: provide run on all cpu but self semanticsAaron Durbin
In order to provide richer semantics for running code on all CPUs add an all-but-self construct. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218652 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9082 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize SCR_EL3 on all CPUsAaron Durbin
Provide SCR_EL3 initialization on all CPUs. This settings were chosen in such a way that nothing would need to be done if EL3 is abandoned after transitioning to EL2 or EL1. If persistent EL3 program is used those SCR policies can be updated within that program. BUG=chrome-os-partner:31634 BRANCH=None TEST=Built and booted through kernel. Printed out SCR setting for each CPU. Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90 Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218300 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9078 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Make exceptions use the transition libraryFurquan Shaikh
Transition library acts as a common interface for handling exceptions. The only thing that needs to be implemented by exception.c is the exc_dispatch routine to handle the exceptions as required. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested using test_exc Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425 Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add useful macro definitions for register bitsFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Coreboot compiles successfully Change-Id: I1fba44974314effa1065e3637aaa5430584a4cc6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a4791232de764ebe40d9b3de5c63479dec7da003 Original-Change-Id: I95fdff5d1580faf4cb4f85d6acae7a834b8ff0bf Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions for writing sp_elxFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions with el argumentFurquan Shaikh
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for read and write registers at current EL in assemblyFurquan Shaikh
In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216373 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove soc_secondary_cpu_init()Aaron Durbin
The original purpose of soc_secondary_cpu_init() was to provide a way for the SoC to run code on the secondary processors as they come up. Now that devicetree based bringup is supported there's no need to have this functionality. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP into linux. Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216927 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add devicetree based CPU startupAaron Durbin
This adds SMP bring up support for arm64 cpus. It's reliant on DEVICE_PATH_CPU devices in the devicetree. Then for each enabled device it attempts to start then initialize each CPU. Additionally, there is a cpu_action construct which allows for running actions on an individual cpu. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted both cores on ryu into linux. Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216925 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: split cpu.h headerAaron Durbin
Add a cpu-internal.h for internal prototypes to the architecture specific code. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted. Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9 Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9041 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add spinlock implementationAaron Durbin
Provide a simple spinlock implentation for arm64. A value of 0 is unlocked and a value of 1 is locked. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup on ryu. Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9040 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: move spinlock.h to proper placeAaron Durbin
The spinlock header file was not residing in the correct place. It needs to live under 'arch/smp'. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with SMP. spinlock.h found. Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0 Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9039 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: provide API for coordinating secondary CPU bringupAaron Durbin
Provides a minimal API for coordinating with the SoC for bringing up the secondary CPUs. There's no eventloop or dispatcher currently nor does it do anything proper when one of the secondary CPUs are brought up. Those decisions are deferred to the SoC. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu using this API. Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376 Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214775 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9019 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add exception_hwinit()Aaron Durbin
exception_hwinit() provides a path for just setting the hardware state. This allows for other CPUs but the boot CPU for setting up the appropriate vector table. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted to the kernel. Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1 Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: make mmu_enable() use previous ttb from mmu_init()Aaron Durbin
No need to pass in the same value for the ttb after just calling mmu_init(). All current users are setting this once and forgetting it. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted on ryu. Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8 Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214772 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: include stack storage within ramstageAaron Durbin
Instead of defining the stacks by Kconfig options include the stack sizes for all the CPUs including each of their exception stacks. This allows for providing each CPU on startup a stack to work with. Note: this currently inherits CONFIG_STACK_SIZE from x86 because of the Kconfig mess of options not being guarded. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted into the kernel on ryu. Change-Id: Ie5fa1a8b78ed808a14efeb1717b98d6b0dd85eef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6524993f016aac2ac8cd9dba9fbdd9a59260a2b6 Original-Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214669 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9013 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add smp_processor_id() declarationAaron Durbin
In order to accomodate MP on arm64 one needs to be able to determine the current logical processor id. Because it depends on the SoC implementation the SoC needs to provide this implementation. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: I2f09df9bf7d4f829d8f45471bf7281a4ddba2fc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6033e73d70c3b8296b36ff36b4b848b176917e12 Original-Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214663 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=test_exception generates a page fault which is handled by the exception handler and execution continues after eret from the exception Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213661 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: handle non-cacheable normal memoryAaron Durbin
Non-cacheable normal memory is needed when one wants an easy way to have a DMA region. That way all the reads and writes will be picked up by the CPU and the device without any cache management operations. BUG=chrome-os-partner:31293 BRANCH=None TEST=With a bevy of other patches can use a carved out DMA region for talking to USB. Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6 Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212160 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13armv8: Add mmu supportFurquan Shaikh
Add support for initializing and enabling mmu for armv8. Using 64KiB granule and 33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes use of memrange library to get a list of all the mmap regions from the SoC to initialize XLAT table. Currently, all calculations in mmu.h are based on the assumptions that max 33 bits are used in VA and granule size is 64KiB. Changes in these assumptions will have to reflect in the dependent calculations as well. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until "payload not found". Goes past all the earlier alignment errors. Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285 Reviewed-on: http://review.coreboot.org/8646 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-03-02coreboot arm64: Correct cache function namesFurquan Shaikh
Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 Reviewed-on: http://review.coreboot.org/8469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25coreboot arm64: Add library for system accessFurquan Shaikh
Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d Reviewed-on: http://review.coreboot.org/8465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-14arm64: Cleanup arch io header filesFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203142 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48 Reviewed-on: http://review.coreboot.org/8410 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: Marc Jones <marc.jones@se-eng.com>
2014-09-23coreboot arm64: Add support for arm64 into coreboot frameworkFurquan Shaikh
Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support The ramstage support is the only portion that has been tested on actual hardware. Bootblock and romstage support may require modifications to run on hardware. Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6915 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 08:59:23 +0000