aboutsummaryrefslogtreecommitdiff
path: root/src/arch/arm64/armv8
AgeCommit message (Collapse)Author
2015-03-30build system: provide generic compiler flag variablesPatrick Georgi
Introduce generic-$(type)-ccopts and $(class)-generic-ccopts to declare compiler flags that apply to all files of a certain type or of a certain class. Then use them. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I655688e82a0cc5bad89b6f55dc217b9f66b64604 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28armv8/secmon: SECMON_SRC is really SECMON_BINPatrick Georgi
It points to a binary. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9113 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: remove EL and mode from secmon_paramsAaron Durbin
Since PSCI dynamically determines which EL to transition to based on SCR_EL3 there's no need to provide that information. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel with MP. Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218924 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add psci support to secmonAaron Durbin
The PSCI functionality initially includes CPU_ON and CPU_OFF functions. Upon entering secmon if the parameters are non-NULL then a PSCI CPU_ON action is done for the current CPU. BUG=chrome-os-partner:32112 BRANCH=None TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel using PSCI. Turned CPUs on and off. Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748 Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218923 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: Provide secmon trampoline for restartAaron Durbin
If an exception is taken that the secmon won't return to, there needs to be way to reset that cpu's state w.r.t. stack usage. Therefore, provide secmon_trampoline which will reinitialize the exception stack and SP_EL0 and start executing with SP_EL0 like the initial state of the secmon entry. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also tested when PSCI is employed in the kernel. Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5 Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218922 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9096 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28arm64: fix smc bugs in secmonAaron Durbin
Two things: 1. Not returning once setting the return state. 2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x)) With these 2 changes arguments and results are being processed correctly. BUG=chrome-os-partner:32112 BRANCH=None TEST=Built and brought up SMP using PSCI. Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8 Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9094 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add smc layer to secmonAaron Durbin
In order to process PSCI commands SMC instructions need to be serviced. Provide a simple way for users of SMC to register their handlers by function. The SMC layer hooks into the exception processing, however it only processes AARCH64 SMC calls. All others are ignored. BUG=chrome-os-partner:32112 BRANCH=None TEST=Added nop smc call to depthcharge. SMC handled and continue booting to kernel. Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30 Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218846 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9092 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: initialize secmon environmentAaron Durbin
The exception vectors were not reinitialized in secmon yet. Add that as well as the split BSP vs non-BSP path. In doing so bring in the cpu.c semantics for determining bsp at runtime. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted to kernel. Also noted only one CPU printing messages. Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32 Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218845 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9091 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: exception handler registrationAaron Durbin
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: add spin table supportAaron Durbin
There was a hacky and one-off spin table support in tegra132. Make this support generic for all arm64 chips. BUG=chrome-os-partner:32082 BRANCH=None TEST=Ran with and without secure monitor booting smp into the kernel. Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748 Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218654 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9084 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Add support for secure monitorFurquan Shaikh
Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Make exceptions use the transition libraryFurquan Shaikh
Transition library acts as a common interface for handling exceptions. The only thing that needs to be implemented by exception.c is the exc_dispatch routine to handle the exceptions as required. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and exceptions are tested using test_exc Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425 Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217143 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Reinit free_idx to 1 in mmu_initFurquan Shaikh
If mmu_init is called more than once then, free_idx should be reset to 1. Here, the assumption would be that mmu_init will not be called more than once. However, this is not necessarily true. Thus, free_idx should be reset to 1 every time we are initializing ttb from scratch. BUG=None BRANCH=None TEST=Compiles sucessfully and boots to kernel Change-Id: I5ac0af43346a492583380b0f15101390fc98d182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56 Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216906 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64: Replace CONFIG_* variables with {read/write}_currentFurquan Shaikh
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions for writing sp_elxFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28arm64 libhelpers: Add helper functions with el argumentFurquan Shaikh
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add more barrier supportAaron Durbin
The load-acquire/store-release operations (including exclusive variants) form a basis for atomic operations. Also remove the dmb, dsb, and isb functions from lib_helpers as barrier.h already included these. Lastly, utilize barrier.h. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and ran SMP bringup using barriers. Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118 Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216921 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9038 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0 Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216920 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9037 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add midr_el1 accessor functionAaron Durbin
Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add exception_hwinit()Aaron Durbin
exception_hwinit() provides a path for just setting the hardware state. This allows for other CPUs but the boot CPU for setting up the appropriate vector table. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted to the kernel. Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1 Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: make mmu_enable() use previous ttb from mmu_init()Aaron Durbin
No need to pass in the same value for the ttb after just calling mmu_init(). All current users are setting this once and forgetting it. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted on ryu. Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8 Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214772 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: add config options for exception level startupAaron Durbin
Depending on the armv8 implementation the cpus could start in EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate mode. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: I8787fd1bc4e14f03d829e6a5e5af915e29314770 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb6b092a43e34fbc64d941bb62f19a6b8ac2c5de Original-Change-Id: Id063681ef7691097e528c105fffac5d467585e4e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214666 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9010 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: Make exceptions workFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=test_exception generates a page fault which is handled by the exception handler and execution continues after eret from the exception Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213661 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26arm64: handle non-cacheable normal memoryAaron Durbin
Non-cacheable normal memory is needed when one wants an easy way to have a DMA region. That way all the reads and writes will be picked up by the CPU and the device without any cache management operations. BUG=chrome-os-partner:31293 BRANCH=None TEST=With a bevy of other patches can use a carved out DMA region for talking to USB. Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6 Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212160 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20bootblocks: use run_romstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_romstage() to perform the necessary work to load and run romstage. Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17rmodules: Make rmodules inclusion for vboot dependent on romstage_archFurquan Shaikh
Currently, the rmodules inclusion for vboot is dependent on ramstage_arch. This change adds dependency on romstage_arch, since vboot is associated with romstage. Inclusion based on ramstage_arch is left as is in case someone needs it in ramstage. BUG=chrome-os-partner:30784 BRANCH=None TEST=Compiles successfully for link, rush and nyan Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209568 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc Reviewed-on: http://review.coreboot.org/8673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13armv8: Add mmu supportFurquan Shaikh
Add support for initializing and enabling mmu for armv8. Using 64KiB granule and 33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes use of memrange library to get a list of all the mmap regions from the SoC to initialize XLAT table. Currently, all calculations in mmu.h are based on the assumptions that max 33 bits are used in VA and granule size is 64KiB. Changes in these assumptions will have to reflect in the dependent calculations as well. BUG=chrome-os-partner:30688 BRANCH=None TEST=Compiles rush successfully and boots until "payload not found". Goes past all the earlier alignment errors. Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285 Reviewed-on: http://review.coreboot.org/8646 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-03-13armv8: correct dcache line size calculationAaron Durbin
The CCSIDR_EL1 register has cache attribute information for a given cache selection in CSSELR_EL1. However, the cache isn't being selected before reading CCSIDR_EL1. Instead use CTR_EL0 which better fits with the semantics of dcache_line_bytes(). CTR_EL0 has the minimum data cache line size of all caches in the system encoded in 19:16 encoded as lg(line size in words). BUG=None TEST=Built. Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208720 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0 Reviewed-on: http://review.coreboot.org/8642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04arm64: use one stage_entry for all stagesAaron Durbin
Ramstage needs an assembly entry point for setting up the initial state of the CPU. Therefore, a function is provided, arm64_el3_startup(), that bootstraps the state of the processor, initializes the stack pointer, and branches to a defined entry symbol. To make this work without adding too much preprocessor macro conditions provide _stack and _estack for all the stages. Currently the entry point after initialization is 'main', however it can be changed/extended to do more work such as seeding the stack contents with tombstones, etc. It should be noted that romstage and bootblock weren't tested. Only ramstage is known to work. BUG=chrome-os-partner:29923 BRANCH=None TEST=Brought up 64-bit ramstage on rush. Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207262 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949 Reviewed-on: http://review.coreboot.org/8585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02coreboot arm64: Correct cache function namesFurquan Shaikh
Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 Reviewed-on: http://review.coreboot.org/8469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25coreboot arm64: Add library for system accessFurquan Shaikh
Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d Reviewed-on: http://review.coreboot.org/8465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-27vboot2: add verstageStefan Reinauer
This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf Reviewed-on: http://review.coreboot.org/8224 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26arm64: Prepare ARM64 for buildingMarc Jones
There were a number of issues with the ARM64 build files. This patch ports the following changes from ARMV4/V7 to ARMV8: - make armv8 Kconfig options consistent with armv4/v7 - fix build include issues in boot.c, tables.c, and early_variables.h by matching armv4/v7. Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iacd95d336559c45458784d1da67bde62a0956620 Reviewed-on: http://review.coreboot.org/8236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-23coreboot arm64: Add support for arm64 into coreboot frameworkFurquan Shaikh
Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support The ramstage support is the only portion that has been tested on actual hardware. Bootblock and romstage support may require modifications to run on hardware. Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6915 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-24 23:34:24 +0000