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For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I63bbac225662377693ad5f29cc8911494c49b422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Linux v6.3.5 is able to detect and use ACPI tables on an out of tree
target using hacked version of u-boot to pass ACPI through UEFI.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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_STR should return Unicode string. From ACPI spec:
6.1.10 _STR (String)
The _STR object evaluates to an Unicode string that describes the
device or thermal zone.
BUG=NA
TEST=Check the changed _STR in SSDT to see if Unicode() macro is used
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables"
XSDT is primarily used to add new tables or to find the S3 resume vector.
However with QEMU coreboot does not generate most ACPI tables but takes
them from whatever QEMU provides. Qemu only creates an RSDT and lacks an
XSDT.
To keep the codebase simple with the assumption that XSDT is always
present, create an XSDT based on the existing RSDT and update the
address in RSDP.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When
creating the dpn array, the length was set to MAX - MIN or 13, numbered
0 to 12.
When accessing the array, the code was bailing out if a value greater
than MAX was trying to be accessed, so the array was able to be overrun
by two structure lengths.
Fix this problem by:
1) Not subtracting the MIN value when creating the array, which does
waste a little space. If anyone wants to refactor the code to fix that,
please feel free.
2) Breaking out of the loop when the port is equal to the MAX port
number instead of just when it's greater than the max port number.
Reported-by: Coverity (CID:1429766 & CID:1429771)
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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Allow the use of 64bit MMCONF base in MCFG table.
Previously only 32 bits were utilized for MMCONF base, while the
remaining 32bits were reserved & held value of zero as evident from MCFG
table disassembly. This commit entails updating the 'base_address' field
in the 'mmconfig' structure to 64 bits and removing the 'base_reserved'
field.
TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG
table disassembly below
Signature : "MCFG"
Table Length : 0000003C
Revision : 01
Checksum : BD
Oem ID : "COREv4"
Oem Table ID : "COREBOOT"
Oem Revision : 00000000
Asl Compiler ID : "CORE"
Asl Compiler Revision : 20230628
Reserved : 0000000000000000
Base Address : 0000001010000000
Segment Group Number : 0000
Start Bus Number : 00
End Bus Number : FF
Reserved : 00000000
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.
Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Allows cbmem console log and timestamps to be read from Windows.
TEST=build/boot Win11 on google/eve, read cbmem log
Change-Id: I545ce43d4337dd71afedda6bc9208a8c3bf158ee
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77139
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.
TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.
Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.
This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76070
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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TESTED acpixtract -a is able to extract all the dumped tables including
FACS and DSDT.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I84ab0068e8409a5e525ddc781347087680d80640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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It's not expected that non-x86 arch implement x86 style sleep states and
resume.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ica6b2d79d61558706998edbbaee185125ff5b36c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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acpi.c contains architectural specific things like IOAPIC, legacy IRQ,
DMAR, HPET, ... all which require the presence of architectural headers.
Instead of littering the code with #if ENV_X86 move the functions to
different compilation units.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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With arm64 -Wstack-usage= is enabled which is triggered on any use of
alloca(). Since this function basically works on x86 without wrecking
things and causing massive stack consumption it's unlikely to cause
problems on arm64.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.
As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix regression introduced with commit 01af0f8ac803 ("acpi/acpi.c: Reduce boilerplate").
DSDT table is not to be listed within RSDT/XSDT, ACPICA and/or OSPM may
try load it twice raising conflicts in the namespace and effectively ignoring all or most of the AML.
Change-Id: I0e6d07b35522f2bf9a51cef0a7e3181b15087d88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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This reduces boilerplate. One functional difference is that SSDT no
longer has oem_revision set to 42.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Adding tables to R/XSDT, aligning current pointer, computing checksum is
a lot of boilerplate that needs to be done for each table.
TESTED on foxconn/g41.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This was missed recently when adding the table. Linux complains about
the missing checksum, e.g.
[ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173)
Tested with QEMU/Q35, albeit with changes to the special handling for
ACPI with QEMU. The warning goes away.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 90464073e4a1 (acpi: Add SPCR table)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TESTED works on IO and MMIO console with linux using 'earlycon=' in the
commandline argument.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75685
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The sign of 'char' is not standardized and with GCC is architecture
dependent.
This fixes warnings when compiling this file on arm64.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I53b99835b2ffec5d752fc531fd59e4715f61aced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Returning a constant value makes the function easier to read and think
about.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifdf7acec38a7c958aac2cf1f3bbf16c27fa90b8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75903
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The argument is copied into current and is never modified.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3084e43ccbe9749bc726af3120decfe8b52e1709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75902
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Loop over tables in xsdt instead of maintaining a list of local
variables to loop over. Some tables were not generated directly in the
write_acpi_tables function, like IVRS or SRAT. Now those tables are
printed too and the code is simpler.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie0a6e2b6e2b72b5c8f59e730bea9b51007b507b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75860
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Sometimes systems don't boot to the OS due to wrong ACPI tables.
Printing the tables in an ACPICA compatible format makes analysis of
ACPI tables easier.
The ACPICA format (acpidump, acpixtract) is the following:
"
FACS @ 0x0000000000000000
0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$......
0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
"
To achieve analyze ACPI tables capture the coreboot log between
"Printing ACPI in ACPICA compatible table" and "Done printing ACPI in
ACPICA compatible table". Remove the prefix "[SPEW ] " and then call
'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on
the .dat files to decompile the tables.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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When an IO resource producer is generated that covers the whole IO space
from 0 to 0xffff, the length field in the word resource ACPI type would
overflow and be truncated which results in Linux not finding any usable
IO space to use for the PCI IO BARs. Instead generate a double word IO
resource producer to have all cases supported. Beware that covering all
IO ports with the IO resource producer while covering the PCI config IO
ports with a resource consumer in the same PCI root device will make
Linux a bit unhappy and it will complain due to the overlap, but still
end up doing the right thing:
acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored
The SoC code should make sure to carve out the PCI config IO ports from
the IO resource producer.
TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord
resource producer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very
clear that they are generating resource producer ranges and not resource
consumer ranges. To clarify this, change the function names to
acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the
ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this
doesn't change the functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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Add the acpigen_resource_mmio helper function to generate an MMIO range
resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I38d55dfcc2892bcb5d253a3aef6ed993cfdba0a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Make ACPI code print a debug warning message when a timeout is
detected in a loop waiting for a condition.
This timeout message won't be displayed when this function is used as
delay loop (ie. without checking variable condition).
The following is required to get this log in kernel log buffer:
echo 1 > /sys/module/acpi/parameters/aml_debug_output
Here is an example of generated code when waiting for variable L23E to
be 0.
Local7 = 0x08
While ((Local7 > Zero))
{
If ((L23E == Zero))
{
Break
}
Sleep (0x10)
Local7--
If ((Local7 == Zero))
{
Debug = "WARN: Wait loop timeout for variable L23E"
}
}
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that the Debug print is added to the
function.
Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Generate formatted string and ACPI code to print debug string.
For example (with pcie_rp = 1):
acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp);
generates the following ACPI code:
Debug = "calling _ON for RP: 1"
With this new function, the following functions are not needed anymore
and therefore are removed by this patch.
- acpigen_concatenate_string_string()
- acpigen_concatenate_string_int()
- acpigen_write_debug_concatenate_string_string()
- acpigen_write_debug_concatenate_string_int()
BRANCH=firmware-brya-14505.B
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot. Check the debug messages is in the
kernel log when /sys/modules/acpi/parameters/aml_debug_output is
set to '1'.
Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Since it's not obvious, add comments to acpigen_resource_word,
acpigen_resource_dword and acpigen_resource_qword to clarify out what
the magic number in byte 0 means. The most significant bit of byte 0
indicates if it is a small or large resource data type. In the case of
the MSB being 0, it's a small resource data type (aka type 0), and the
other bits encode bit the type and size of the item; if the MSB is 1,
it's a large resource data type (aka type 1), and the other bits just
encode the type and there are two separate bytes to encode the size.
Beware that the large resource's data type values in the ACPI
specification don't include the MSB that's set, but only the 7 lower
bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add the acpigen_resource_io helper function to generate an I/O range
resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
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Add the acpigen_resource_bus_number helper function to generate a bus
number range resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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At present coreboot_rsdp remains unset for QEMU, which results in
an incomplete LB_TAG_ACPI_RSDP coreboot table generated.
Fix this by assigning coreboot_rsdp properly.
TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86
as the payload, boot coreboot.rom with QEMU, and run 'acpi list'
from U-Boot shell to show the ACPI tables.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
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Introduce acpigen_write_BBN to generate the ACPI method object that
returns the base bus number for a PCI(e) host bridge. When called, the
base_bus_number argument must be the first PCI bus number that got
assigned to the corresponding host bridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
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cbfs_map() can allocate memory, so cbfs_unmap() should be
called before leaving the function.
BUG=b:278264488
TEST=Built and run with additional debugs on Skyrim device
to confirm that data are correctly unmapped
Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
|
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This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.
There were no reference for the use of offset 0x48 for century.
Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.
Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.
Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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According to ACPI Release 6.5 systems supporting PIC (i8259)
interrupt mechanism need to report IRQ vector for the SCI_INT
field. In PIC mode only IRQ0..15 are allowed hardware vectors.
This change should cover section 5.2.9 to not pass SCI_INT
larger than IRQ15. Section 5.2.15.5 needs follow-up work.
Care should be taken that ioapic_get_sci_pin() is called
after platform code has potentially changed the routing
from the default.
It appears touched all platforms except siemens/mc_aplX
currently program SCI as IRQ9.
Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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These functions are only used in one compilation unit.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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After the obsoletion of Processor() it is necessary to provide
_PTC package to define P_CNT IO address for clock throttling.
The platforms touched here already emit empty _PTC to disable
clock throttling.
Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74438
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After the obsoletion of Processor() it is necessary to provide
_CST package to define P_LVLx IO addresses for C2/C3 transitions.
The latency values from _CST will always replace those in FADT.
Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.
Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.
For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.
Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Secondary threads need to be added after the primary threads.
Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e.
Add multiple fan support for dptf policies.
This also fixes the Google Meet resolution drop issue as per
b:246535768 comment#12. When system starts Google Meet video call,
it uses the hardware accelerated encoder as expected. But, as soon as
another system connects to the call, an immediate fallback is observed
from hardware to software encoder. Due to this, Google Meet resolution
dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC
based fanless platforms. This same issue was not seen on fan based
systems. With the fix in dptf driver where fan configures appropriate
setting for only fan participant, not for other device participants,
able to see consistent 720p resolution.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alder Lake-P Redrix system for two fans
support and on Alder Lake-N fanless systems. With this code change
Google Meet resolution drop not observed.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This avoids some code duplication related to X2APIC mode.
Change-Id: I592c69e0f52687924fe41189b082c86913999136
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
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This avoids some code duplication related to X2APIC mode.
Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
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Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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For platforms using X2APIC mode add SRAT x2APIC table
generation. This allows to setup proper SRAT tables.
Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The PPCC method should return the package, but is missing the return
statement, leading to DPTF/S0ix to not function properly. Add the
required return statement.
TEST=build/boot Win11 on google/banshee, verify DPTF, S0ix functional.
Change-Id: I051db7d69dd6cdfbb07caf649247ee166c1c74ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72921
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Use existing functions instead of open-coding the same functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie35c7e0fd3caa25b0d3d02443609e54dd2fdcb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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acpigen_write_rom open-codes this functionality, so add a function for
this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use existing functions instead of open-coding the same functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660bd5d357eb86c19a5a7847925f6176c3fb4425
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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1. add functions to generate if greater than conditions:
acpigen_write_if_lgreater_op_op:
if (op1 > op2)
acpigen_write_if_lgreater_op_int:
if (op > val)
acpigen_write_if_lgreater_namestr_int:
if (namestr > val)
2. add function to assignal value to a namestr
acpigen_write_store_namestr_to_op:
namestr = val
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI Revision 6.0 deprecates Processor keyword, so use
acpigen_write_processor_device() instead.
Change-Id: I31626f4e323dd9053a63c0f5e89d1685103e4bd4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in
ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP
with the special HID ACPI0007 should be used instead. This special HID
was introduced in version 3 of the ACPI spec. To have a function to
generate this, acpigen_write_processor_device is introduced. The CPU
index is used as UID which can be assumed to be unique.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This functionality is used in multiple places, so factor it out into a
function. Compared to acpigen_write_processor_cnot, the buffer size is
decreased from 40 to 16 bytes, but the format string specified by
CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit
into the buffer without any issue. I've seen the CPU devices being put
into another scope within \_SB, but even in that case that would be 14
chars and a NULL byte whist still fits into the 16 byte buffer. For
acpigen_write_processor and acpigen_write_processor_package this doesn't
change any edge case behavior. In the unrealistic case of the format
string resulting in a longer CPU device string, this would have been a
problem before this patch too.
Also drop the curly braces of the for loop in
acpigen_write_processor_package. This makes the code a bit harder to
read and isn't a very good idea, but with the curly braces in place, the
linter breaks the build :(
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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ACPI_CPU_STRING specifies the format string for the scope of the
processor devices in the generated ACPI code. Also point out that the
resulting string will be truncated to at most 15 chars to fit into the
16 byte buffer used in two functions in acpigen.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fb1db8adeecd783c835a500d28a13b823cda155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72451
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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add functions for concatenate OP
add debug message containing concatenated string with string, value, or
OPs
Ex1: to print string with another string provided from C side:
acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=",
name, LOCAL6_OP);
will generate:
Concatenate ("Wait loop Timeout! var=", "L23E", Local6)
Debug = Local6
Ex2: to print string with a value:
acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:",
pcie_rp, LOCAL0_OP);
will generate:
Concatenate ("ModPHY enabling for RP:", 0x05, Local0)
Debug = Local0
Ex3: to print string with an ACPI OP:
acpigen_write_debug_concatenate_string_op("while Loop count: ",
LOCAL7_OP, LOCAL6_OP)
will generate:
Concatenate ("while Loop count: ", Local7, Local6)
Debug = Local6
TEST=Add above functions in the acpigen code and check the generated
SSDT table after OS boot
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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This patch supports projects to use _DSM to control USB3 U1/U2
transition per port.
More details can be found in
https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
The ACPI and USB driver of linux kernel need corresponding functions
to support this feature. Please see
https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
BUG=b:253402457
TEST=tested on felwinter and found _DSM method is created.
Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reads back the ioapic id from hardware.
Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70267
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update SRAT table revision to 3 according to ACPI spec.
Add CEDT table revision according to CXL spec.
Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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BUG=b:259716145
TEST=Verified SSDT on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70063
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create a common method to add DmaProperty.
BUG=b:259716145
TEST=Verified SSDT on google/osiris.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I75b3f22ad29f90f3c3b251bd0d70bae9d75f71fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These boards do no fill MADT with useful information.
Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.
Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69818
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.
Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).
TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Update the default processor sting from decimal to hex to increase
the default number of Processor NamedObjects from 100 to 256
ie: CP00-CP99 is now CP00-CPFF
This fixes MADT table generation for system up to 256 cores.
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: Id60a39d99fa77d1d89ad655ddecdebcc8a422f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Without a cast the aritmetics of
tat = einj + sizeof(acpi_einj_smi_t)
is the same as
tat = (uintptr_t)einj + size(acpi_einj_smi_t) * size(acpi_einj_smi_t)
So it overshoots the intended offset by a lot.
This issue only came apparent because now einj is in the small IMD
region which is close to TSEG. With the wrong aritmetics the tat
pointer ended up inside TSEG which is not accessible from the OS
causing exceptions.
TEST: observe that tat pointer is inside the small IMD below
TSEG (0x78000000 on our setup).
"acpi_create_einj trigger_action_table = 0x77ffe89c"
Change-Id: I3ab64b95c33eef01b2048816a21e17855bcb2f54
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Read I/O APIC ID and vector counts from hardware.
Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It will be used in a follow-up change.
Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd.
Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.
Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.
TEST: compile test and qemu run successfully with coreinfo
payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.
TEST: compile tested and qemu emulation successfully run
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add multiple fan support for dptf policies
BUG=b:235254828
BRANCH=None
TEST=Built and tested on Redrix system for two fans
Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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hardwaremain.c is the common ramstage entry to all platforms so move
out ACPI code generation (x86 specific) to boot state hooks.
Another reason to do this is the following:
On some platforms that start in dram it makes little sense to have
separate stages. To reduce the complexity we want to call the ramstage
main function instead of loading a full stage. To make this scheme
more maintainable it makes sense to move out as much functionality
from the 'main' function as possible.
Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63414
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the device has enabled `use_gpio_for_status`, then call the `_STA`
method in `_ON` to determine if the device is already enabled. If it is
already enabled, return early to skip re-enabling the device and
performing the associated sleep.
This change is necessary since the Linux kernel does not call `_STA`
before calling `_ON`.
BRANCH=None
BUG=b:225022810
TEST=Dump SSDT table for guybrush
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I13aa41766555953b86eded4c72e3b317fe6db5c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add
support for TBAT device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TBAT device
Device (TBAT)
{
Name (_HID, "INTC1061") // _HID: Hardware ID
Name (_UID, "TBAT") // _UID: Unique ID
Name (_STR, "Battery Participant") // _STR: Description String
Name (PTYP, 0xC)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
Add support for TPWR device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device
Device (TPWR)
{
Name (_HID, "INTC1060") // _HID: Hardware ID
Name (_UID, "TPWR") // _UID: Unique ID
Name (_STR, "Power Participant") // _STR: Description String
Name (PTYP, 0x11)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service
On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.
This also adds the respective unit test.
Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These helpers are not architecture dependent and it might be used for
different platform.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All SoCs/chipsets that select ARCH_X86 will end up using the
implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the
unused weak implementation that returns a different value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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