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2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-24device: Add inline method to identify PATH_ROOTPatrick Rudolph
Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-24acpi,arch,commonlib: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice5dadd3eaadfa9962225520a3a75b05b44518ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/80066 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-22device/device.h: Drop acpi_inject_dsdtArthur Heymans
This is now unused in the tree and filling SSDT should always be used. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-16device: Add support for multiple PCI segment groupsFelix Held
Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-01-13acpi/acpigen: add acpigen_write_SEG for segment group number methodFelix Held
Introduce acpigen_write_SEG to generate the ACPI method object that returns the PCI segment group number for a PCI(e) host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20acpi: Reduce wait interval in delay loop for sleepSukumar Ghorai
The optimization of sleep time in acpi code includes reducing the sleep duration and increasing the polling frequency within the acpi _ON/_OFF method. StorageD3Enable is activated in Google/Rex, and this optimization results in a saving of approximately 25ms in D3cold resume time, reducing it from around 160ms to 135ms. BUG=b:296206467 BRANCH=firmware-rex-15709.B TEST=boot test verified on google/rex verified _ON/_OFF Method in SSDT. verifid kernel log in s0ix test - 0000:00:06.0: PM: pci_pm_resume_noirq Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-12-15acpi: Add support for WDAT tableMarek Maslanka
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog Action Table) table specification. The WDAT is a special ACPI table introduced by Microsoft that describes the watchdog for the OS. Platforms that need to implement the WDAT table must describe the hardware watchdog management operations as described in the specification. See “Links to ACPI-Related Documents” (http://uefi.org/acpi) under the heading “Watchdog Action Table”. BUG=b:314260167 TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes successfully. Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-12-08acpi.c: Fix generating pointer to cb_tables located >4GArthur Heymans
Use the generic resource_consumer method which works for memory both above and below 4G. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1bc553b18d08cee502b765166227810f8e619631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76181 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-07acpi: add missing device/device.h includeFelix Held
The device/device.h provides the definition for struct device used in those files, so include this header file to make sure that it's not only included indirectly via some other header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-06acpi/acpi_gic: Add GIC ITS subtableNaresh Solanki
Add support for generating GIC subtable ITS (Interrupt Translator Service). Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06acpi: Add IO Remapping Table structuresNaresh Solanki
Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-05acpi/acpi: make sure that table_ptr is non-NULL in acpidump_printFelix Held
While acpidump_print shouldn't be called with a NULL pointer as table_ptr argument, better add a check to not end up dereferencing the NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-02acpi: Add PPTT supportDavid Milosevic
This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-02soc/amd: Add DBG2 ACPI tableZheng Bao
Dump the DBG2 table on Linux console. $> acpidump -s ACPI: DBG2 0x0000000000000000 000054 (v00 COREv4 COREBOOT 00000000 **) $> acpidump > acpidump.bin $> acpixtract -a acpidump.bin $> iasl -d dbg2.dat $> cat dbg2.dsl /* * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000054 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : FA [00Ah 0010 6] Oem ID : "COREv4" [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 20220331 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0028 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0002 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0012 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 006612] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FEDC9000 [04Eh 0078 4] Address Size : 00000100 [052h 0082 2] Namepath : "." Raw Table Data: Length 84 (0x54) 00: 44 42 47 32 54 00 00 00 00 FA 43 4F 52 45 76 34 // DBG2T.....COREv4 10: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 20: 31 03 22 20 2C 00 00 00 01 00 00 00 00 28 00 01 // 1." ,........(.. 30: 02 00 26 00 00 00 00 00 00 80 12 00 00 00 16 00 // ..&............. 40: 22 00 00 00 00 03 00 90 DC FE 00 00 00 00 00 01 // "............... 50: 00 00 2E 00 // .... BUG=b:303689867 Change-Id: I3c97a78d1889549421baf0bc1a2e8f959a0f47e2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79174 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27acpi: Enable 64bit ECAM resourceNaresh Solanki
Adjust ACPI DSDT to support ECAM resource above 4GB by modifying the PCI ECAM Resource Consumption settings. The changes include specifying a QWordMemory resource template, accommodating non-cacheable, read-write attributes, and adjusting the address range. Change-Id: Idb049d848f2311e27df5279a10c33f9fab259c08 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-23acpigen.c: Add resource consumer functions for mmioArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id9e4adcd976e1f56ef7f502d9df16dbefce95c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79217 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16acpi/device: Only return dev->ops->acpi_name if non-NULLCoolStar
Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-15acpi/acpigen: drop len assert in acpigen_pop_lenFelix Held
This is already handled as a separate case in the code below, so there's no need for this assert any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTESFelix Held
Use a define instead of magic numbers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15acpi/acpigen: rework acpigen_pop_len for different size PkgLengthFelix Held
Previously acpigen_pop_len always wrote a 3 byte PkgLength to the 3 bytes reserved by acpigen_write_len_f. After this patch acpigen_pop_len encodes PkgLength in 1-3 bytes depending on the PkgLength. When less than the 3 bytes that were previously reserved in the corresponding acpigen_write_len_f call are needed for PkgLength, the payload data will be moved back by the number of reserved bytes that aren't needed for the PkgLength. This fixes the problem that the Windows AML parser doesn't like a 3 byte PkgLength being used for the size of the buffer containing UTF-16 strings when the length could be encoded in a single PkgLength byte. In that case, Windows previously ignored the whole SSDT containing this larger than necessary PkgLength encoding. It should however be noted that the ACPI 6.4 spec doesn't specify if it's required to always use the most compact possible encoding of the PkgLength or not. Since iasl generates the shortest possible PkgLength encoding, it's also a good idea to make coreboot's acpigen do the same although it's not required by the specification. With this patch applied, Windows still boots on Mandolin and the time it takes to write the tables doesn't change. To measure the times, the log level in bs_sample_time was increased to BIOS_CRIT and the console log level was increased to BIOS_CRIT too to only get those times as output. BS: BS_WRITE_TABLES run times (exec / console): 8 / 0 ms Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-11-13acpi/acpigen: point out what acpigen_write_len_f doesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf2f54f2f428f4438ef22b7f9d205db10e144db Reviewed-on: https://review.coreboot.org/c/coreboot/+/79001 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-11acpi/acpigen: Fix buffer length in acpigen_write_name_unicode()Matt DeVillier
The buffer length is in bytes, and since we are converting from ASCII to UTF-16, the value written needs to be 2x the string length + null terminator. TEST=build/boot google skyrim (frostflow), dump acpi and check bytecode for correct buffer length preceding unicode strings. Change-Id: Id322e3ff457ca1c92c55125224ca6cfab8762a84 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-16acpi/acpigen: Allow general namestring in write mutex functionsPaweł Anikiel
BUG=b:301150499 TEST=Compiled and tested on google/redrix - PERST# goes low when wwan modem goes into runtime suspend. Change-Id: Ib09d5a6091cedfce24da49390cf980414f97a2c9 Signed-off-by: Paweł Anikiel <panikiel@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-10-02acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punctJonathon Hall
Librem 11's volume keys act as a PS/2 keyboard with only those two keys. Reduce the minimum number of top-row keys to 2. Make the "rest of keys" (alphanumerics, punctuation, etc.) optional. Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-27acpi: Fix typosNaresh Solanki
Change-Id: Ie986c1cbbc9bcc7817dfeb04a4be86898b302987 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-18acpi: Add functions to declare ARM GIC V3 hardwareArthur Heymans
For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18acpi/Makefile.inc: Move code inclusionArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I63bbac225662377693ad5f29cc8911494c49b422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-09-18arch/arm64: Hook up ACPI table generationArthur Heymans
Linux v6.3.5 is able to detect and use ACPI tables on an out of tree target using hacked version of u-boot to pass ACPI through UEFI. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-09-14acpi: Comply with ACPI specification by making _STR unicode stringsCliff Huang
_STR should return Unicode string. From ACPI spec: 6.1.10 _STR (String) The _STR object evaluates to an Unicode string that describes the device or thermal zone. BUG=NA TEST=Check the changed _STR in SSDT to see if Unicode() macro is used Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-14acpi.c: Add XSDT on QEMUArthur Heymans
Since d8f2dce "acpi.c: Swap XSDT and RSDT for adding/finding tables" XSDT is primarily used to add new tables or to find the S3 resume vector. However with QEMU coreboot does not generate most ACPI tables but takes them from whatever QEMU provides. Qemu only creates an RSDT and lacks an XSDT. To keep the codebase simple with the assumption that XSDT is always present, create an XSDT based on the existing RSDT and update the address in RSDP. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia9b7f090f55e436de98afad6f23597c3d426bb88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77385 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-13acpi/soundwire.[ch]: Fix dpn entry array overrunMartin Roth
In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When creating the dpn array, the length was set to MAX - MIN or 13, numbered 0 to 12. When accessing the array, the code was bailing out if a value greater than MAX was trying to be accessed, so the array was able to be overrun by two structure lengths. Fix this problem by: 1) Not subtracting the MIN value when creating the array, which does waste a little space. If anyone wants to refactor the code to fix that, please feel free. 2) Breaking out of the loop when the port is equal to the MAX port number instead of just when it's greater than the max port number. Reported-by: Coverity (CID:1429766 & CID:1429771) Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-09-01acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG tableNaresh Solanki
Allow the use of 64bit MMCONF base in MCFG table. Previously only 32 bits were utilized for MMCONF base, while the remaining 32bits were reserved & held value of zero as evident from MCFG table disassembly. This commit entails updating the 'base_address' field in the 'mmconfig' structure to 64 bits and removing the 'base_reserved' field. TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG table disassembly below Signature : "MCFG" Table Length : 0000003C Revision : 01 Checksum : BD Oem ID : "COREv4" Oem Table ID : "COREBOOT" Oem Revision : 00000000 Asl Compiler ID : "CORE" Asl Compiler Revision : 20230628 Reserved : 0000000000000000 Base Address : 0000001010000000 Segment Group Number : 0000 Start Bus Number : 00 End Bus Number : FF Reserved : 00000000 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24acpi: Add function to add ARM PL011 to ACPI DBG2Arthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-13src/acpi/acpi.c: make BOOT0000 APCI device visible to OSMatt DeVillier
Allows cbmem console log and timestamps to be read from Windows. TEST=build/boot Win11 on google/eve, read cbmem log Change-Id: I545ce43d4337dd71afedda6bc9208a8c3bf158ee Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77139 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03acpi.c: Find FACS using 64bit address fieldsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-03acpi.c: Swap XSDT and RSDT for adding/finding tablesArthur Heymans
If ACPI is above 4G it's not possible to have a valid RSDT pointer in RSDP, therefore swap RSDT and XSDT. Both are always generated on x86. On other architectures RSDT is often skipped, e.g. aarch64. On top of that the OS looks at XSDT first. So unconditionally using XSDT and not RSDT is fine. This also deal with the ACPI pointer being above 4G. This currently never happens with x86 platforms. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6588676186faa896b6076f871d7f8f633db21e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-02acpi/acpi.c: Move setting FADT SCI INT to arch specific codeArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-08-02acpi/acpi.c: Add and use acpi_arch_fill_madt()Arthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76070 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-02acpi.c: Add FACS and DSDT to debug hex printingArthur Heymans
TESTED acpixtract -a is able to extract all the dumped tables including FACS and DSDT. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-02acpi.c: Fill in >4G FADT entries correctlyArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-02acpi.c: Guard FACS generationArthur Heymans
It's not expected that non-x86 arch implement x86 style sleep states and resume. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-23acpi.c: Add functions to create GTDTArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ica6b2d79d61558706998edbbaee185125ff5b36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21acpi/acpi.c: Split of ACPI table generation into separate filesArthur Heymans
acpi.c contains architectural specific things like IOAPIC, legacy IRQ, DMAR, HPET, ... all which require the presence of architectural headers. Instead of littering the code with #if ENV_X86 move the functions to different compilation units. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21acpi/acpigen.c: Ignore compiler warning about stack overflowingArthur Heymans
With arm64 -Wstack-usage= is enabled which is triggered on any use of alloca(). Since this function basically works on x86 without wrecking things and causing massive stack consumption it's unlikely to cause problems on arm64. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-20acpi: Move ECAM resource below PNP0C02 device in a common placeArthur Heymans
From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06acpi/acpi.c: Fix regression with DSDTKyösti Mälkki
Fix regression introduced with commit 01af0f8ac803 ("acpi/acpi.c: Reduce boilerplate"). DSDT table is not to be listed within RSDT/XSDT, ACPICA and/or OSPM may try load it twice raising conflicts in the namespace and effectively ignoring all or most of the AML. Change-Id: I0e6d07b35522f2bf9a51cef0a7e3181b15087d88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-03acpi/acpi.c: Move ACPI header creation to a functionArthur Heymans
This reduces boilerplate. One functional difference is that SSDT no longer has oem_revision set to 42. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-03acpi/acpi.c: Reduce boilerplateArthur Heymans
Adding tables to R/XSDT, aligning current pointer, computing checksum is a lot of boilerplate that needs to be done for each table. TESTED on foxconn/g41. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-06-29acpi: Set checksum for SPCR tableNico Huber
This was missed recently when adding the table. Linux complains about the missing checksum, e.g. [ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173) Tested with QEMU/Q35, albeit with changes to the special handling for ACPI with QEMU. The warning goes away. Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Fixes: commit 90464073e4a1 (acpi: Add SPCR table) Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28acpi: Add SPCR tableArthur Heymans
TESTED works on IO and MMIO console with linux using 'earlycon=' in the commandline argument. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75685 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26acpi/acpigen.c: Be explicit about char signArthur Heymans
The sign of 'char' is not standardized and with GCC is architecture dependent. This fixes warnings when compiling this file on arm64. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I53b99835b2ffec5d752fc531fd59e4715f61aced Reviewed-on: https://review.coreboot.org/c/coreboot/+/76006 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18acpi/acpi.c: Return function argument when bailing outArthur Heymans
Returning a constant value makes the function easier to read and think about. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifdf7acec38a7c958aac2cf1f3bbf16c27fa90b8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75903 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18acpi/acpi.c: Change signature of write_acpi_tablesArthur Heymans
The argument is copied into current and is never modified. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3084e43ccbe9749bc726af3120decfe8b52e1709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75902 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17acpi/acpi.c: Fix printing all ACPI tablesArthur Heymans
Loop over tables in xsdt instead of maintaining a list of local variables to loop over. Some tables were not generated directly in the write_acpi_tables function, like IVRS or SRAT. Now those tables are printed too and the code is simpler. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie0a6e2b6e2b72b5c8f59e730bea9b51007b507b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75860 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-06-14acpi: Add a debug option to print out tables in ACPICA compatible hexArthur Heymans
Sometimes systems don't boot to the OS due to wrong ACPI tables. Printing the tables in an ACPICA compatible format makes analysis of ACPI tables easier. The ACPICA format (acpidump, acpixtract) is the following: " FACS @ 0x0000000000000000 0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$...... 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ " To achieve analyze ACPI tables capture the coreboot log between "Printing ACPI in ACPICA compatible table" and "Done printing ACPI in ACPICA compatible table". Remove the prefix "[SPEW ] " and then call 'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on the .dat files to decompile the tables. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12acpi/acpi.c: Reduce scope of functions used locallyArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-07acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_ioFelix Held
When an IO resource producer is generated that covers the whole IO space from 0 to 0xffff, the length field in the word resource ACPI type would overflow and be truncated which results in Linux not finding any usable IO space to use for the PCI IO BARs. Instead generate a double word IO resource producer to have all cases supported. Beware that covering all IO ports with the IO resource producer while covering the PCI config IO ports with a resource consumer in the same PCI root device will make Linux a bit unhappy and it will complain due to the overlap, but still end up doing the right thing: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored The SoC code should make sure to carve out the PCI config IO ports from the IO resource producer. TEST=Both Ubuntu 2022.04.1 LTS and Windows 10 are ok with the IO DWord resource producer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8a59cdfcfa30a8fdd13f8db3dc1447994c266c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-30acpi/acpigen: rename and clarify bus/IO/MMIO resource producer functionsFelix Held
The acpigen_resource_[bus_number,io,mmio*] functions didn't make it very clear that they are generating resource producer ranges and not resource consumer ranges. To clarify this, change the function names to acpigen_resource_producer_[bus_number,io,mmio*] and explicitly add the ADDR_SPACE_GENERAL_FLAG_PRODUCER flag which evaluates to 0, so this doesn't change the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I334f38aa8ab418d5577f92b980ff750504e2bb4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-26acpi/acpigen: add acpigen_resource_mmio to generate MMIO resourceFelix Held
Add the acpigen_resource_mmio helper function to generate an MMIO range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I38d55dfcc2892bcb5d253a3aef6ed993cfdba0a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-17acpi: Warn on timeout in write_delay_until()Cliff Huang
Make ACPI code print a debug warning message when a timeout is detected in a loop waiting for a condition. This timeout message won't be displayed when this function is used as delay loop (ie. without checking variable condition). The following is required to get this log in kernel log buffer: echo 1 > /sys/module/acpi/parameters/aml_debug_output Here is an example of generated code when waiting for variable L23E to be 0. Local7 = 0x08 While ((Local7 > Zero)) { If ((L23E == Zero)) { Break } Sleep (0x10) Local7-- If ((Local7 == Zero)) { Debug = "WARN: Wait loop timeout for variable L23E" } } BRANCH=firmware-brya-14505.B TEST=Boot to OS and check that the Debug print is added to the function. Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16acpigen: Add printf-like function for debug stringCliff Huang
Generate formatted string and ACPI code to print debug string. For example (with pcie_rp = 1): acpigen_write_debug_sprintf("calling _ON for RP: %u", pcie_rp); generates the following ACPI code: Debug = "calling _ON for RP: 1" With this new function, the following functions are not needed anymore and therefore are removed by this patch. - acpigen_concatenate_string_string() - acpigen_concatenate_string_int() - acpigen_write_debug_concatenate_string_string() - acpigen_write_debug_concatenate_string_int() BRANCH=firmware-brya-14505.B TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot. Check the debug messages is in the kernel log when /sys/modules/acpi/parameters/aml_debug_output is set to '1'. Change-Id: Id4a42e5854516a22b7bc4559c2ed08680722c5ba Signed-off-by: Cliff Huang <cliff.huang@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Musse Abdullahi <musse.abdullahi@intel.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-14acpi/acpigen: add comment about byte 0 in acpigen_resource_*wordFelix Held
Since it's not obvious, add comments to acpigen_resource_word, acpigen_resource_dword and acpigen_resource_qword to clarify out what the magic number in byte 0 means. The most significant bit of byte 0 indicates if it is a small or large resource data type. In the case of the MSB being 0, it's a small resource data type (aka type 0), and the other bits encode bit the type and size of the item; if the MSB is 1, it's a large resource data type (aka type 1), and the other bits just encode the type and there are two separate bytes to encode the size. Beware that the large resource's data type values in the ACPI specification don't include the MSB that's set, but only the 7 lower bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held
In ACPI 1.0 the processor objects were inside the \_PR scope, but since ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS compatibility, but apart from that the \_PR scope is deprecated. coreboot already uses the \_SB scope for the processor devices everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the format string inside the 3 snprintf statements that use the ACPI_CPU_STRING. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-11acpi/acpigen: add acpigen_resource_io to generate I/O resourceFelix Held
Add the acpigen_resource_io helper function to generate an I/O range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I177f59b52d4dbbff0a3ceeef5fc8c7455cef9ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11acpi/acpigen: add acpigen_resource_bus_number to generate bus numberFelix Held
Add the acpigen_resource_bus_number helper function to generate a bus number range resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib1f1da3dbe823c6bc4fc30c0622653410cfbf301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-11acpi/acpi.c: Assign coreboot_rsdp for QEMUBin Meng
At present coreboot_rsdp remains unset for QEMU, which results in an incomplete LB_TAG_ACPI_RSDP coreboot table generated. Fix this by assigning coreboot_rsdp properly. TEST=Build coreboot for QEMU x86 i440fx (default) with U-Boot x86 as the payload, boot coreboot.rom with QEMU, and run 'acpi list' from U-Boot shell to show the ACPI tables. Signed-off-by: Bin Meng <bmeng@tinylab.org> Change-Id: I5bc3f0528d4431fd388ca52b8865f9be0e1faf92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-08acpi/acpigen: add acpigen_write_BBN to generate base bus number methodFelix Held
Introduce acpigen_write_BBN to generate the ACPI method object that returns the base bus number for a PCI(e) host bridge. When called, the base_bus_number argument must be the first PCI bus number that got assigned to the corresponding host bridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib67bf42b9c77c262d8a02d8f28ac5cb8482136b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-01acpi: Add missing cbfs_unmap()Grzegorz Bernacki
cbfs_map() can allocate memory, so cbfs_unmap() should be called before leaving the function. BUG=b:278264488 TEST=Built and run with additional debugs on Skyrim device to confirm that data are correctly unmapped Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-01acpigen: Add a runtime method to override exposed _Sx sleep statesArthur Heymans
This allows mainboards to override available sleep states at runtime. This is done by adding a IntObj in SSDT that DSDT consumes to override the available _Sx states. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADTKyösti Mälkki
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms' implementations of adding IOAPIC and IRQ override entries for ACPI MADT tables. Platforms that have a more complex MADT may continue to add custom entries using CUSTOM_ACPI_MADT. Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add acpigen_write_PTC()Kyösti Mälkki
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26acpi/acpi.c: Reduce scope of some functionsArthur Heymans
These functions are only used in one compilation unit. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-21ACPI: Obsolete FADT duty_offset and duty_width fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _PTC package to define P_CNT IO address for clock throttling. The platforms touched here already emit empty _PTC to disable clock throttling. Change-Id: I0e84c8ccd2772c9b3d61f71b74324c8d28f4eefe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74438 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14acpi/acpi.c: Follow spec more closely for MADTArthur Heymans
Secondary threads need to be added after the primary threads. Change-Id: I3a98560760b662a7ba7efb46f5f7882fb0f7bb1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11ACPI: Add helper for MADT LAPICsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11ACPI: Add helper for MADT LAPIC NMIsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11binaryPI: Use common code for LAPIC NMIsKyösti Mälkki
Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-03-03acpi: Add SRAT x2APIC table supportNaresh Solanki
For platforms using X2APIC mode add SRAT x2APIC table generation. This allows to setup proper SRAT tables. Change-Id: If78c423884b7ce9330f0f46998ac83da334ee26d Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-14acpi/acpigen_dptf: Add pkg return to dptf_write_power_limits()CoolStar
The PPCC method should return the package, but is missing the return statement, leading to DPTF/S0ix to not function properly. Add the required return statement. TEST=build/boot Win11 on google/banshee, verify DPTF, S0ix functional. Change-Id: I051db7d69dd6cdfbb07caf649247ee166c1c74ac Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72921 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-10acpi/acpigen: use acpigen_write_store_* in acpigen_write_romFelix Held
Use existing functions instead of open-coding the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie35c7e0fd3caa25b0d3d02443609e54dd2fdcb7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10acpi/acpigen: add acpigen_write_store_namestr_to_namestrFelix Held
acpigen_write_rom open-codes this functionality, so add a function for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-10acpi/acpigen: use acpigen_write_if_lgreater_* in acpigen_write_romFelix Held
Use existing functions instead of open-coding the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I660bd5d357eb86c19a5a7847925f6176c3fb4425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-09src/acpi: add function gen: if_lgreater_ and namestr assignmentCliff Huang
1. add functions to generate if greater than conditions: acpigen_write_if_lgreater_op_op: if (op1 > op2) acpigen_write_if_lgreater_op_int: if (op > val) acpigen_write_if_lgreater_namestr_int: if (namestr > val) 2. add function to assignal value to a namestr acpigen_write_store_namestr_to_op: namestr = val TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07acpi/acpigen.c: Add a comment to deprecate acpigen_write_processor()Elyes Haouas
ACPI Revision 6.0 deprecates Processor keyword, so use acpigen_write_processor_device() instead. Change-Id: I31626f4e323dd9053a63c0f5e89d1685103e4bd4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31acpi/acpigen: introduce acpigen_write_processor_deviceFelix Held
The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP with the special HID ACPI0007 should be used instead. This special HID was introduced in version 3 of the ACPI spec. To have a function to generate this, acpigen_write_processor_device is introduced. The CPU index is used as UID which can be assumed to be unique. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-28acpi/acpigen: factor out acpigen_write_processor_namestringFelix Held
This functionality is used in multiple places, so factor it out into a function. Compared to acpigen_write_processor_cnot, the buffer size is decreased from 40 to 16 bytes, but the format string specified by CONFIG_ACPI_CPU_STRING results in 9 chars and a NULL byte which will fit into the buffer without any issue. I've seen the CPU devices being put into another scope within \_SB, but even in that case that would be 14 chars and a NULL byte whist still fits into the 16 byte buffer. For acpigen_write_processor and acpigen_write_processor_package this doesn't change any edge case behavior. In the unrealistic case of the format string resulting in a longer CPU device string, this would have been a problem before this patch too. Also drop the curly braces of the for loop in acpigen_write_processor_package. This makes the code a bit harder to read and isn't a very good idea, but with the curly braces in place, the linter breaks the build :( Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d8291a2aaae2011cb185d72c7f7864b6e2220ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/72452 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-28acpi/Kconfig: improve description of ACPI_CPU_STRING config optionFelix Held
ACPI_CPU_STRING specifies the format string for the scope of the processor devices in the generated ACPI code. Also point out that the resulting string will be truncated to at most 15 chars to fit into the 16 byte buffer used in two functions in acpigen.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1fb1db8adeecd783c835a500d28a13b823cda155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72451 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-27src/acpi: add debug message with concatenated stringCliff Huang
add functions for concatenate OP add debug message containing concatenated string with string, value, or OPs Ex1: to print string with another string provided from C side: acpigen_write_debug_concatenate_string_string("Wait loop Timeout! var=", name, LOCAL6_OP); will generate: Concatenate ("Wait loop Timeout! var=", "L23E", Local6) Debug = Local6 Ex2: to print string with a value: acpigen_write_debug_concatenate_string_int("ModPHY enabling for RP:", pcie_rp, LOCAL0_OP); will generate: Concatenate ("ModPHY enabling for RP:", 0x05, Local0) Debug = Local0 Ex3: to print string with an ACPI OP: acpigen_write_debug_concatenate_string_op("while Loop count: ", LOCAL7_OP, LOCAL6_OP) will generate: Concatenate ("while Loop count: ", Local7, Local6) Debug = Local6 TEST=Add above functions in the acpigen code and check the generated SSDT table after OS boot Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I370745efe3d6b513ec2c5376248362a3eb4b3d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72126 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-01-19drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per portKane Chen
This patch supports projects to use _DSM to control USB3 U1/U2 transition per port. More details can be found in https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- The ACPI and USB driver of linux kernel need corresponding functions to support this feature. Please see https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm BUG=b:253402457 TEST=tested on felwinter and found _DSM method is created. Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 01:23:39 +0000