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2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16src/acpi: Add missing <types.h>Elyes HAOUAS
Change-Id: Iec78183b43ea26d9de14e0ce28eef6fc0361cc95 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-01-28acpi/acpigen.c: Remove unused and incorrect functionsJakub Czapiga
acpigen_write_name_zero() and acpigen_write_name_one() are not implemented correctly, and are not used anywhere. Drop them in favor of the more flexible acpigen_write_name_integer() function. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I116fd41624a8e8b536d18d747f21d3131b734dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-02src/acpi/acpigen: Add NULL pointer checkRonak Kanabar
Add NULL pointer check in acpigen_emit_namestring to avoid segmentation fault. Change-Id: I3d01d28e74f202278b5a5a96d2edd45c66f10883 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48148 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09acpigen: Add more useful helper functionsDuncan Laurie
acpigen_write_debug_namestr() - Debug = NAME acpigen_write_return_namestr() - Return (NAME) acpigen_set_package_op_element_int() - Set package pointer element DeRefOf (PKG[ELEM]) = INT acpigen_get_package_element() - Get package (not pointer) element dest_op = PKG[ELEM] acpigen_set_package_element_int() - Set package element to integer PKG[ELEM] = INT acpigen_set_package_element_namestr() - Set package element to namestr PKG[ELEM] = NAME acpigen_write_delay_until_namestr_int() - Delay while waiting for register to equal expected value. BUG=b:160996445 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I9b20a23872b7d4a50f03761032426ffbb722b9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/47196 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04soc/intel/skl,acpi/acpigen: convert global CPPC package to local oneMichael Niewöhner
Move the global CPPC package \GCPC to the first logical core CP00 and adapt the reference in the other cores. This is cleaner and avoids confusion. Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-21acpigen: Make acpigen_write_opregion() argument constDuncan Laurie
This structure is not modified so it can be made const and allow the calling function to also declare it as a const structure. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Make gpio set/get arguments constDuncan Laurie
The 'struct acpi_gpio' arguments passed to acpigen functions are not modified so they can be made const, which allows drivers to also use a const pointer. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add ShiftLeft function helperDuncan Laurie
Provide a helper function for the ACPI shift left operator that uses the same operator for the source and result. ShiftLeft (OP, count, OP) Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add helpers for common Store operationsDuncan Laurie
Add helpers for some store operations: Store(INTEGER, NAME) ex: Store (100, SAVE) Store(INTEGER, OP) ex: Store (100, Local0) Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21acpigen: Add option for reserved bits in FieldDuncan Laurie
Add an option for unused/reserved bits in a Field definition, allowing for declarations that do not start at bit 0: Field (UART, AnyAcc, NoLock, Preserve) { , 7, /* RESERVED */ BITF, /* Used bit */ } These just use byte 0 instead of a name. Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22acpi: Add SSDT pstate helper functionsJason Glenesk
Add new generic helper functions for PSS, PCT, XPSS, objects. BUG=b:155307433 TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear as expected and conform to ACPI_6_3_May16.pdf ACPI specification. Check XPSS against Microsoft "Extended PSS ACPI Method Specification" XPSS_spec.doc April 2, 2007. BRANCH=Zork Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-15acpi: Correct sizes for ACPI data fieldsJason Glenesk
Correct sizes of Count, Type, and Latency data field in _CST object to integer, byte, word, respectively. Correct size of NumEntries data field in _CSD object to integer. BUG=b:155307433 TEST=Boot Morphius and dump SSDT _CST and _CSD objects. Confirm that sizes written conform to ACPI_6_3_May16.pdf ACPI specification. BRANCH=Zork Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45339 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24src/acpi: Drop unneeded empty linesElyes HAOUAS
Change-Id: I561717c9ee3471462ee510f12c821cfe236b23be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-21acpi: add more AML generation functionsAaron Durbin
Add the following functions to acpi AML generation code: acpigen_write_to_integer_from_namestring() acpigen_write_create_byte_field() acpigen_write_create_word_field() acpigen_write_create_dword_field() acpigen_write_create_qword_field() BUG=b:163583825 Change-Id: Ida151aff68f90012b16df2383fb96ddb87c3fb9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44641 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18src/acpi/acpigen.c: Use macro for access_sizeElyes HAOUAS
Change-Id: I677d055b3cd47f760d743a6ecb63cb5738274090 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-07acpigen: Add acpigen_notifyTim Wawrzynczak
A fairly common thing in ACPI is notifying a device when some kind of device-specific event happens; this function simplifies writing this pattern. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42102 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07acpi: add STA function to return external variableSugnan Prabhu S
This change adds support function to add STA function which returns an external variable. Change-Id: I31755a76ee985ee6059289ae194537d531270761 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42245 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-02acpi_device: Replace polarity with active_low in acpi_gpio for GpioIoFurquan Shaikh
As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-03acpigen: Add some new helper functionsDuncan Laurie
These build on existing functions but use different object types in order to provide functions for upcoming changes: acpigen_write_return_op(): Return an operator. acpigen_write_if_lequal_op_op(): Check if 2 operands are equal. acpigen_get_package_op_element(): Read an element from a package into an operator. This one just provides the missing helper, the other 3 already exist: acpigen_get_tx_gpio: Read TX gpio state. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I1141fd132d6f09cf482f74e95308947cba2c5846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41985 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21acpi/device: Add a helper function to write SoundWire _ADRDuncan Laurie
This change adds a help function to write a SoundWire ACPI address object that conforms to the SoundWire DisCo Specification Version 1.0 The SoundWire address structure is defined in include/device/soundwire.h and provides the properties that are used to form the _ADR object. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I6efbf52ce20b53f96d69efe2bf004b98dbe06552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02acpi: Move ACPI table support out of arch/x86 (1/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 1/5 which moves .c files from arch/x86 to acpi/. The only acpi files that are still retained under arch/x86 are: a. acpi_s3.c: This doesn't really deal with ACPI tables. Also, there are some assumptions in there about SMM which will have to be resolved if this file needs to be moved to common code. b. acpi_bert_storage.c/bert_storage.h: This file is currently written specifically with x86 in mind. So, not moving the file for now. Motivation for this change: Not all stages on Picasso SoC are targeted for the same architecture. For example, verstage (if runs before bootblock) will be targeted for non-x86. This makes it difficult to add device tree to verstage which would be required to get to SoC configs from the tree. This is because the device tree on x86 platforms currently contains a lot of devices that require ACPI related enums and structs (like acpi_gpio, acpi_pld, acpi_dp and so on). Hence, this change removes all ACPI table support out of arch/x86. BUG=b:155428745 Change-Id: Icc6b793c52c86483a8c52e0555619e36869a869e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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