| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-09-27 | acpi: Fix typos | Naresh Solanki | |
| Change-Id: Ie986c1cbbc9bcc7817dfeb04a4be86898b302987 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> | |||
| 2023-09-18 | acpi: Add functions to declare ARM GIC V3 hardware | Arthur Heymans | |
| For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
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