summaryrefslogtreecommitdiff
path: root/spd
AgeCommit message (Collapse)Author
2022-03-10spd/lp5: Add new part MT62F2G32D8DR-031Amanda Huang
Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-02-24spd/lp4x: Generate initial SPD for MT53E2G32D4NQ-046 WT:CWisley Chen
Generate the initial SPD for MT53E2G32D4NQ-046 WT:C BUG=b:220804962 TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I3e2b377f1d6d4b1fa45614ad2f3de81eef17c2b8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian
ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-15spd/lp5: Add new part H9JCNNNBK3MLYR-N6EReka Norman
Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-10spd/lp5: Generate initial SPDs for Sabrina SoCKarthikeyan Ramasubramanian
Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03spd: Add new LP5 part Samsung K3LKBKB0BM-MGCPReka Norman
Samsung K3LKBKB0BM-MGCP will be used by the nissa variant nereid. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:197479026 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I4db983d5015a4dacad0bd03cf7a85f6214856a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-08spd: Add new LP5 parts and generate SPDsReka Norman
Add the parts below which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. Micron MT62F512M32D2DR-031 WT:B Micron MT62F1G32D4DR-031 WT:B Hynix H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05spd: Add lp5 directory with empty memory_parts fileReka Norman
Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23spd: Add SPD for 4JQA-0622AD to spd/Reka Norman
Since generating the SPDs under spd/, a new part was added in https://review.coreboot.org/57550. Regenerate the SPDs to include this new part. Commands used: cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie673d1a386479f690182050ce4fee7d252ec9530 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23util/spd_tools: Remove PLK platformReka Norman
Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23lib/Makefile.inc: Generate placeholder spd.bin in lib/Makefile.incReka Norman
When a new variant is created, it needs to have a path to its SPD binary defined. Currently, this is done by setting SPD_SOURCES to a placeholder SPD file, which just contains zero bytes. To remove the need for a placeholder file, automatically generate a single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the marker value 'placeholder'. BUG=b:191776301 TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build and check that spd.bin contains a single zero byte. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-20spd: Add a placeholder SPD file to spd/Reka Norman
When a new variant is created, its SPD_SOURCES contains a placeholder file, to avoid a build failure due to SPD_SOURCES being empty. Currently these placeholder files live with the rest of the SPD files in soc and mainboard directories, e.g. src/soc/intel/alderlake/spd/placeholder.spd.hex Add a similar placeholder SPD file to the new spd/ directory. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia6d76ed512a7e44221fc93ad960790be575c44c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-20spd: Generate SPDs under spd/ using unified spd_gen toolReka Norman
Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 15:14:43 +0000