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2022-06-17spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCPLeo Chou
This adds support for Samsung K3LKCKC0BM-MGCP LP5 chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=None BUG=235664831 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I49cea0594f8a94aa7efbb375ea1c28b5d1136498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-03spd/lp5: Add SPD for Micron MT62F1G32D4DSCaveh Jalali
This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-02spd/lp5: Add new LP5 part H58G56AK6BX069Terry Chen
Hynix H58G56AK6BX069 will be used by the brya variant crota. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:233830713 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6136e17706c6248598886f8f9bd8fdd7efff4dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-31spd: Add new LP5 part Samsung K3LKLKL0EM-MGCNTyler Wang
Samsung K3LKLKL0EM-MGCN will be used by the nissa variant craask. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:229938024 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5648f297130eaf8541d99b2db7777774a0b1d8fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-10spd/lp5: Add new part MT62F2G32D8DR-031Amanda Huang
Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian
ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-15spd/lp5: Add new part H9JCNNNBK3MLYR-N6EReka Norman
Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-10spd/lp5: Generate initial SPDs for Sabrina SoCKarthikeyan Ramasubramanian
Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-03spd: Add new LP5 part Samsung K3LKBKB0BM-MGCPReka Norman
Samsung K3LKBKB0BM-MGCP will be used by the nissa variant nereid. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:197479026 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I4db983d5015a4dacad0bd03cf7a85f6214856a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-08spd: Add new LP5 parts and generate SPDsReka Norman
Add the parts below which will be used by the brya variant Vell. Add the parts to memory_parts.json and generate the SPDs using spd_gen. Micron MT62F512M32D2DR-031 WT:B Micron MT62F1G32D4DR-031 WT:B Hynix H9JCNNNCP3MLYR-N6E Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: Ifbcadfb78281b2b78a61a9b61180c421748193a0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05spd: Add lp5 directory with empty memory_parts fileReka Norman
Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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