| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-03-08 | util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) | Karthikeyan Ramasubramanian |
| 2022-02-17 | util/spd_tools/spd_gen/lp5: Encode Bank Architecture | Karthikeyan Ramasubramanian |
| 2022-02-17 | util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features | Karthikeyan Ramasubramanian |
| 2022-02-15 | spd/lp5: Add new part H9JCNNNBK3MLYR-N6E | Reka Norman |
| 2022-02-10 | spd/lp5: Generate initial SPDs for Sabrina SoC | Karthikeyan Ramasubramanian |
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index : coreboot.git | |
| my copy of coreboot | User & |
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