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2022-10-28spd/lp5: Re-generate the SPD dataEricKY Cheng
Re-generate Hynix H58G66BK7BX067 and H58G56BK7BX068 data with current spd_tools. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I19ae0477dea64f2cdd37b6aa51eadd6957c54059 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-20spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6EFrank Wu
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate the SPD. BUG=b:250470704 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2022-10-13spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068EricKY Cheng
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the memory_parts.json and re-generate the SPD. BUG=b:243337816 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-09-29util/spd_tools: Change Mendocino to use 0x13 for LP5x memory typeRobert Zieba
Mendocino supports LP5x but currently doesn't support SPDs that use the LP5x memory type, 0x15. This commit updates set 1 SPDs, which are currently only used for mendocino, to use 0x13 for their memory type. BUG=b:245509394 TEST=Generated SPDs, verified that only set 1 have changed to 0x13 Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-08-30mb/google/skyrim/var/winterhold: Update Lp5x and Lp5 memory supportEricKY Cheng
Update K3KL8L80CM-MGCT, K3KL9L90CM-MGCT,H58G66AK6BX070 support BRANCH=None BUG=b:243337816 TEST= SPD add Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I2c370fbd007c22b1f94074d9f16e5bc7c4e04848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-25util/spd_tools: Add support for LP5X SPDsRobert Zieba
This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-01util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian
Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-29spd/lp5: Add SPD for Micron MT62F2G32D4DS-026Tarun Tuli
This adds support for Micron MT62F2G32D4DS-026 chips. BUG=b:240289148 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1212506d742178803a7e7bf7e0236d1095f7af9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-19util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-14spd/lp5: Add support for MT62F1G32D2DS-026 WT:BJack Rosenthal
Datasheet is available in the bug. BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Iadd4bf07d38dbd2e1f47df5024282b04dec3c805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65795 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCPLeo Chou
This adds support for Samsung K3LKCKC0BM-MGCP LP5 chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=None BUG=235664831 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I49cea0594f8a94aa7efbb375ea1c28b5d1136498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-03spd/lp5: Add SPD for Micron MT62F1G32D4DSCaveh Jalali
This adds support for Micron "MT62F1G32D4DS-031 WT:B" LP5 chips. generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BRANCH=none BUG=b:233822309 Change-Id: Idd7fb074c4747a705a1870cd3d4393867289923b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-02spd/lp5: Add new LP5 part H58G56AK6BX069Terry Chen
Hynix H58G56AK6BX069 will be used by the brya variant crota. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:233830713 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I6136e17706c6248598886f8f9bd8fdd7efff4dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-05-31spd: Add new LP5 part Samsung K3LKLKL0EM-MGCNTyler Wang
Samsung K3LKLKL0EM-MGCN will be used by the nissa variant craask. Add it to the LP5 parts list and regenerate the SPDs using spd_gen. BUG=b:229938024 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5648f297130eaf8541d99b2db7777774a0b1d8fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-10spd/lp5: Add new part MT62F2G32D8DR-031Amanda Huang
Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:213926260 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62542 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian
ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-15spd/lp5: Add new part H9JCNNNBK3MLYR-N6EReka Norman
Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts list and regenerate the SPDs using spd_gen. BUG=b:217096008 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I8775fe0551e0712507d42a778e04745a07270d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-10spd/lp5: Generate initial SPDs for Sabrina SoCKarthikeyan Ramasubramanian
Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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