coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-11-13	spd/lp4x: Add SPD for CXDB4CBAM-ML-A in parts_spd_manifest.generated.txt	Daniel Peng
	Generate initial SPD matched for CXMT CXDB4CBAM-ML-A. BUG=b:304932936 TEST=make -C util/spd_tools util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: Ia33a94a1784f865b4776ad9107e25e87420f944f Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78891 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09	spd/lp4x: Generate initial SPD for CXDB4ABAM-ML	Stanley Wu
	Generate initial SPD for CXMT CXDB4ABAM-ML BUG=b:290154780 TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I0de6b128f05abf2fbd4b785818268b69338ed45a Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-06-03	spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL	Wisley Chen
	Generate initial SPD for Samsung K4UCE3Q4AB-MGCL BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-07-28	spd/lp4x: Generate initial SPD for H54G68CYRBX248	Wisley Chen
	Generate initial SPD for H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: Iae75391938446e9ee387b779ddcaa378a23ee52e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24	spd/lp4x: Generate initial SPD for MT53E2G32D4NQ-046 WT:C	Wisley Chen
	Generate the initial SPD for MT53E2G32D4NQ-046 WT:C BUG=b:220804962 TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I3e2b377f1d6d4b1fa45614ad2f3de81eef17c2b8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20	spd: Generate SPDs under spd/ using unified spd_gen tool	Reka Norman
	Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>