summaryrefslogtreecommitdiff
path: root/payloads
AgeCommit message (Collapse)Author
2020-02-05libpayload/xhci: Fix MPS handling in set_addressKangheui Won
We set MPS to speed_to_default_mps(speed) initially but later compare maxpacketsize with 8 to change mps. So compare with speed_to_default_mps(speed) to determine if we need to change settings here. BUG=b:147783572 BRANCH=none TEST=works with 12Mbps/8MPS USB device Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04coreinfo/coreinfo.c: Correct main function signatureJacob Garber
libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14libpayload: cbgfx: Support drawing a box with rounded cornersYu-Ping Wu
A function draw_rounded_box() is added to draw a box with rounded corners. In addition, this function is different from draw_box() in 2 ways: - The position and size arguments are relative to the canvas. - This function supports drawing only the border of a box (linear time complexity when the thickness is fixed). BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-27Makefile: Remove romccElyes HAOUAS
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-20libpayload/drivers/i8042: add error messages to i8042_probeEric Lai
Print error message before error return for better debugging. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/37689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-16libpayload: Implement reading from CBMEM consoleYu-Ping Wu
To support showing CBMEM logs on recovery screen, add a function cbmem_console_snapshot() to copy the CBMEM console to an allocated buffer. Non-printable characters are automatically replaced with '?' to ensure the returned string is printable. BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-13payloads/seabios: Update stable from 1.12.1 to 1.13.0Martin Kepplinger
SeaBIOS 1.13.0 has been tagged on 20191209. Major changes in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups see http://seabios.org/Releases Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-13libpayload/drivers/i8042: Add error handlingEric Lai
Add error handling on I8042_CMD_WR_CMD_BYTE failure. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-12libpayload/drivers/i8042: Remove obsolete flagEric Lai
CB:37594 change the flag makes PC_KEYBOARD_IGNORE_INIT_FAILURE obsolete. Remove it. BUG=b:145130110 TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcf816155b32dd691b48a7479297b556d32dd6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11libpayload/drivers/i8042: Add AT translated Keyboard supportEric Lai
Wilco device uses the AT translated keyboard and doesn't need to set scancode set. Remove the ignore flag and put into translation mode instead. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-09payloads/bayou: remove unhooked payloadAngel Pons
The bayou payload is not attached to the build system in any way, and has not been for quite a while. Since selecting it in Kconfig does nothing, remove this payload now that coreboot 4.10 has been released. Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06endian: Replace explicit byte swapping with compiler builtinJulius Werner
gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-05arm64: Bump exception stack size to 2KBJulius Werner
To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-05trogdor: libpayload USB supportT Michael Turney
Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04mmio: Add clrsetbitsXX() API in place of updateX()Julius Werner
This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot tableYu-Ping Wu
Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-28libpayload: Add BIT(x) macro definitionsatya priya
Add BIT(x) macro definition in libpayload. Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40 Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove imgtec/pistachio SoCJulius Werner
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19mmio: Fix buffer_to_fifo32() order of argumentsJulius Werner
buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but unfortunately its arguments are swapped. This patch fixes the issue. Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-16libpayload: keyboard: Ignore special keysThejaswani Putta
Some special keys emit a prefix scan code 0xE0. We will ignore all these except for the power button, F12 and cursor keys on drallion. Media key mapping is set in depthcharge and will be sent to libpayload keyboard driver. Whichever board requires this change will update its own media key mapping. BUG:b:139511038 TEST=boot in recovery mode, press F12 to go to diagnostic mode and power button to confirm. Also in recovery mode left arrow, right arrow, up arrow, down arrow changes the language on the firmware screen. Change-Id: I1c11939d18391bebe53ca21cf33a096ba369cd56 Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36654 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14Fix sarien depthcharge make buildSelma BENSAID
CONFIG_MAINBOARD_DEPTHCHARGE is set to "" for boards not configuring it. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: If61a1371ad8baf165b09ce045fc1a6c205c2c0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/36336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-12payloads/external/GRUB2: Check for existing grub2 directoryWerner Zeh
When 'make clean' is executed and there is no source code cloned for GRUB2 in payloads/external/GRUB2/grub2 (so GRUB2 has never been used on this tree) an error message is thrown: "fatal: cannot change to 'grub2': No such file or directory" This error happens when there is no grub2 directory and is caused by line 20 in payloads/external/GRUB2/Makefile where a shell command is used to check the state of the git repo for grub2. Thought the target for this code (checkout) is not executed by 'make clean' the shell evaluates the command as part of the Makefile sourcing and encounters a missing directory. This patch fixes this error by checking for the project directory before the git status of the repo is evaluated. Change-Id: Ieaa919e1ee5ec2a1ec3c840fa07a6ec16d230e88 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-11libpayload: usbmsc: update return value of CSW transferChangqi Hu
When the first CSW transfer failed, get_csw function will retry CSW transfer again, but the return value is not updated. Change-Id: I289916baa08d0a189d659164a0002347f6f435db Signed-off-by: Changqi Hu <changqi.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-04payloads/external/GRUB2: fix constantly rebuilding due to git checkoutMichael Niewöhner
Multiple git checkouts cause GRUB2 to constantly rebuild even if there were no changes to code or config. This is due to changing timestamps. Fix this by not creating or switching branches but instead rely on `git checkout -f` which does not touch existing unchanged files. To be sure to not break anyones workflow checkout is skipped and a warning gets printed if the tree/index is unclean. Change-Id: I7cf66f63268de973a654146a0a47c3d5ca516d4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36343 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30libpayload: handle special-class-handlers before sourcesArthur Heymans
This matches the coreboot makefile behavior. Change-Id: Iaada965de904cb03edd068fed8827643496292cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36439 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03libpayload: refactor fetching cbmem pointersPatrick Georgi
There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-02libpayload: Add fmap_cache to sysinfo_tFurquan Shaikh
Now that FMAP is cached in CBMEM and its pointer is added to coreboot table for quick lookup, this change adds a new member "fmap_cache" to sysinfo_t that can be used by payloads to get to FMAP cache. BUG=b:141723751 Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02coreinfo/coreinfo.c: Support both lower and upper case alphabetsHimanshu Sahdev
Modify handle_category_key to handle both upper and lower case alphabets in the coreinfo payload. Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-24depthcharge: add CONFIG_MAINBOARD_DEPTHCHARGESelma BENSAID
CONFIG_MAINBOARD_DEPTHCHARGE is used to override the Board config for depthcharge which inherit from CONFIG_MAINBOARD_PART_NUMBER. This is mainly to avoid depthcharge config duplication. Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I6cbc93ca38ad6deeca2c2fb7770024a24233b6f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-18libpayload: Use interrupt transfers for USB hubsNico Huber
In interactive payloads, the USB stack's poll procedure is implicitly called from the UI loop. Since all USB control transfers are handled synchronously, polling hubs with these slows the UI significantly down. So switch to interrupt transfers that are done asynchronously and only perform control transfers when the hub reported a status change. We use the interrupt endpoint's max packet size instead of the theo- retical transfer length of `(bNrPorts + 1) / 8` as Linux' code mentions hubs that return too much data. Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-15payloads/LinuxBoot: move kernel make flags into own variableAlexander Couzens
Change-Id: I9240043d2c15b68aabe154b289a961d8d48d3e5f Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02payloads/external/LinuxBoot: Add curl flagMarcello Sylvester Bauer
add --show-error curl flag to see the error message, even on silent mode. Signed-off-by: Marcello Sylvester Bauer <sylvblck@sylv.io> Change-Id: I4ad40718caab60413ffe9c1503a9870cb875dd43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-27libpayload/usb: add USB 3.1 GEN2 supportEric Lai
USB 3.1 GEN2 report speed type 4, add into speed enum. BUG=b:139787920 BRANCH=N/A TEST=Build libpayload and depthcharge on sarien and boot with USB GEN2 HUB with USB disk. Check ultra speed device in cbmem log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia0ef12b2f0d91bf0d0db766bbc9019de1614a4f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35023 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22libpayload: usbmsc: Factor out usb_msc_force_init() functionJulius Werner
We're planning to have a use case with a custom USB device that implements the USB mass storage protocol on its bulk endpoints, but does not have the normal MSC class/protocol interface descriptors and does not support class-specific control requests (Get Max LUN and Bulk-Only Reset). We'd like to identify/enumerate the device via usb_generic_create() in our payload but then reuse all the normal MSC driver code. In order to make that possible, this patch factors a new usb_msc_force_init() function out of usb_msc_init() which will initialize an MSC device without checking its descriptors. It also adds some "quirks" flags that allow devices registered this way to customize behavior of the MSC stack. Change-Id: I50392128409cb2a879954f234149a5e3b060a229 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-22libpayload: usbmsc: Skip zero-length packets at end of dataJulius Werner
Some broken USB mass storage devices send another zero-length packet at the end of the data part of a transfer if the amount of data was evenly divisible by the packet size (which is pretty much always the case for block reads). This packet will get interpreted as the CSW and screw up the MSC state machine. This patch works around this issue by retrying the CSW transfer when it was received as exactly 0 bytes. This is the same mitigation the Linux kernel uses and harmless for correctly behaving devices. Also tighten validation of the CSW a little, making sure we verify the length before we read any fields and checking the signature in addition to the tag. Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34485 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22Add buffer_to/from_fifo32(_prefix) helpersJulius Werner
Many peripheral drivers across different SoCs regularly face the same task of piping a transfer buffer into (or reading it out of) a 32-bit FIFO register. Sometimes it's just one register, sometimes a whole array of registers. Sometimes you actually transfer 4 bytes per register read/write, sometimes only 2 (or even 1). Sometimes writes need to be prefixed with one or two command bytes which makes the actual payload buffer "misaligned" in relation to the FIFO and requires a bunch of tricky bit packing logic to get right. Most of the times transfer lengths are not guaranteed to be divisible by 4, which also requires a bunch of logic to treat the potential unaligned end of the transfer correctly. We have a dozen different implementations of this same pattern across coreboot. This patch introduces a new family of helper functions that aims to solve all these use cases once and for all (*fingers crossed*). Change-Id: Ia71f66c1cee530afa4c77c46a838b4de646ffcfb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-21payloads/tianocore: Enable UEFIPayloadLijian Zhao
corebootpayload package in upstream TianoCore was replaced with UEFIPayload, add external payload build option for UEFIPayload. BUG=N/A TEST=Select TianoCore payload as UEFIPayload, build and able to boot up on QEMU q35 after PCIE_BASE set. Change-Id: I0b7785fde9f4113b2cd91323ac0358b229c5a6e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34459 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20Makefile.inc, payloads: Enable -WvlaJacob Garber
Variable length arrays are dangerous, so let's make sure they don't sneak back into coreboot or any of the payloads. Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33846 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/riscv: Enable FIT supportJonathan Neuschäfer
Tested on qemu-riscv. Depends on OpenSBI integration and proper memory detection in qemu. Boots into Linux until initrd should be loaded. Tested on SiFive/unleashed: Boots into Linux until earlycon terminates. Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08libpayload: cbgfx: Allow rotation of the displayNicolas Boichat
Sometimes the display native orientation does not match the device default orientation, so allow rotation of the framebuffer before it is displayed on screen. set_pixel now take coordinates in the rotated coordinate system, and converts the coordinates before writing to the framebuffer. Also, screen.size now matches the rotated system (_not_ the framebuffer size). BUG=b:132049716 TEST=Boot krane, see that FW screen is orientation properly. Change-Id: If9316c0ce33c17057372ef5995a2c68de4f11f02 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-07-26libpayload/serial/qcs405: Mark uart console as suchPatrick Georgi
depthcharge prefers knowing where its input comes from BUG=b:137378326 BRANCH=none TEST=ctrl-d / enter to enter dev-mode works now. Change-Id: I74b5be18c3583be17c73950ced93fad883690090 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-25payloads/external/Yabits: Pass XGCCPATHNico Huber
Pass `XGCCPATH` instead of individual programs as that is what the Makefile expects. Change-Id: I3267ec5259e9d37b2f3b0b8c126d173fc8b5a3ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-23vboot: deprecate vboot_handoff structureJoel Kitching
vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23libpayload/libc: Use size_t for lengths and indicesJacob Garber
size_t is the natural integer type for strlen() and array indices, and this fixes several integer conversion and sign comparison warnings. Change-Id: I5658b19f990de4596a602b36d9533b1ca96ad947 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33794 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23libpayload/libc: Tidy utf16le_to_asciiJacob Garber
- Constify the string argument - Change int to size_t, which is what xmalloc expects Change-Id: I8b5a13319ded4025f883760f2b6d4d7a9ad9fb8b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-23libpayload/libc: Correct strlcat return valueJacob Garber
The documented return value for strlcat is horribly wrong, as is the return value itself. It should not return the number of appended bytes, but rather the length of the concatenated string. From the man page: The strlcpy() and strlcat() functions return the total length of the string they tried to create. For strlcpy() that means the length of src. For strlcat() that means the initial length of dst plus the length of src. While this may seem somewhat confusing, it was done to make truncation detection simple. This change is more likely to fix existing code than break it, since anyone who uses the return value of strlcat will almost certainly rely on the standard behaviour rather than investigate coreboot's source code to see that we have a quirky version. Change-Id: I4421305af85bce88d12d6fdc2eea6807ccdcf449 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-21libpayload: Enable -Wimplicit-fallthroughJacob Garber
Add comments to intentional fall throughs and enable the warning. Change-Id: I93e071c4fb139fa6e9cd8a1bfb5800f5f4eac50b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19payloads/GRUB: Use correct script name in MakefileGompa
Fixes: 3555389a8c (payloads: Update GRUB stable from 2.02 to 2.04) Change-Id: I2f95059453ca5565a38550b147590ece4d8bf5ad Signed-off-by: Gompa <gompa@h-bomb.nl> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-13util/testing: Ensure coreboot-gerrit fails if libpayload build failsKeith Short
The JUnit output from the libpayload builds was getting deleted by the coreinfo build. Move the libpayload to later in the coreboot-gerrit job. Also add messages to stdout indicating the various libpayload configs that are built and a message indicating when all libpayload builds are complete. BUG=b:137380189 TEST=Upload test commit that includes a libpayload compile error and verify buildbot fails. Change-Id: I43b55f402216582dcf81be34171437be345572ab Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13payloads: Update GRUB stable from 2.02 to 2.04Paul Menzel
GRUB 2.04 was released on July 5th, 2019, so update. The only change-log is the git history. Some coreboot related changes are listed below. 1. coreboot: Changed cbmemc to support updated console format from coreboot. 2. ahci: Increase time-out from 10 s to 32 s 3. normal/menu: Do not treat error values as key presses When building from the git repository, `./bootstrap.sh` needs to be run to set up Gnulib. Ignore the exit code, as older versions might not have this script. Change-Id: Iab0b87164ed86f15d3415af935998b59e0d76c45 Signed-off-by: Pablo <42.pablo.ms@gmail.com> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09libpayload/usb: fix DWC2 driverPatrick Georgi
A typo introduced in commit bf2c693f893ab6f9458f1a4840c2a9cbbd4bb9f2 made the driver not build: DWC_SLEEP_TIME_US instead of DWC2_SLEEP_TIME_US. Change-Id: I197b25fd4f568cce7a4bbcee8cc285b25b26afb1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-08payloads/external/Memtest86Plus: update to version 002 stableMartin Kepplinger
The memtest86plus project has been tagged as stable. Update the coreboot build accordingly. Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07payloads/coreinfo: Enable -Wmissing-prototypesJacob Garber
Change-Id: I7ee9436ba71ceea35a35272291ea245c0b7c37c5 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07payloads/coreinfo: Make internal functions staticJacob Garber
These functions are only used in the files they are defined in, so they can be made static. Change-Id: Ic7f78912803cbdd1cb3a75f7f69f526739dab6e7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07payloads/coreinfo: Enable -WextraJacob Garber
This enables extra useful warnings. Change-Id: I3d54988935c7df9ac0dc2f7aceb56fb720c9c4d1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07payloads/coreinfo: Use correct integer types for loop indicesJacob Garber
Make sure that the type of the loop index matches the type of the upper bound. This fixes several -Wsign-compare warnings. Change-Id: I73a88355d86288609e03f7a6fcaec14dfedac203 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07payloads/coreinfo: Use fixed-width integers for cpuidJacob Garber
This function executes the cpuid instruction, which takes a 32 bit input value (idx), and then stores output in eax, ebx, ecx, and edx, which are all 32 bit registers. Update the prototype to use fixed-width integers, and update all usage calls appropriately. Change-Id: I15876fa35628d3a505864fb49be4fdab1fd19f4a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02libpayload/usb: Increase USB request timeout to 5 sKeith Short
Increase the timeout for USB requests to 5 seconds for all USB host controllers. Prior to this fix, the xCHI driver was detecting false timeouts during SET ADDRESS requests when nested downstream hubs were connected to the xHCI root hub. BUG=b:124730179 BRANCH=sarien TEST=Build libpayload and depthcharge on sarien/arcada. TEST=Without change replicate USB set address timeouts in depthcharge when dock and 4K monitor connected (which includes a total of 4 USB hubs). With timeout fix, depthcharge boots OS with no USB errors and the same USB topology. Note that this tests xHCI operation only. Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-29libpayload: cbgfx: Run cbgfx_init() before we need it for draw_box()Julius Werner
calculate_color() uses the 'fbinfo' global that is initialized by cbgfx_init(), so we need to run the latter before we can run the former or we get a null pointer access. Change-Id: I73ca8e20ca36f64d699379d504fd41dc2084f157 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-06-28payloads/external/LinuxBoot: Update x86_64 defconfigPatrick Rudolph
* Add support for Linux 5.x ** Select PCI, which isn't the default anymore with 5.x ** Select google firmware driver, which wasn't build any more * Add support for Intel LPSS uart ** Select MFD and MFD_INTEL_LPSS_PCI ** Increase console count to 32 * Add support for coreboot framebuffer ** Select FB_SIMPLE * Add support for eMMC/SDHCI ** Select MMC_SDHCI_* * Add support for u-root's localboot ** Select KEXEC_FILE_LOAD ** Select FIRMWARE_MEMMAP Stats: * Kernel size 1.9MiB * U-root (core + systemboot) 4.6MiB Tested on Intel APL Up² board: * Fixes non working console on APL Up2 board and eMMC bootmedia shows up. * Allows to boot GNU/Linux from eMMC using 'localboot' Change-Id: Ib5bd33531741e588ac7d5ff6a02b0482f6655ddf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-27libpayload: Re-initialize UART RXPrudhvi Yarlagadda
UART RX needs to be re-initialized in libpayload as it is getting reset at the end of coreboot. Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-21payloads/libpayload: Update a Makefile for sample libpayloadAsami Doi
and make a configuraton for QEMU/ARM. This CL allows building a sample libpayload for QEMU/ARM. Change-Id: Ia32872c43a99357aa966de3582f6fdb2e2652517 Signed-off-by: Asami Doi <doiasami1219@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-18commonlib: define cbtable tags as enum to identify conflictsPatrick Georgi
We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Also add a few values to libpayload that were only defined in commonlib. Change-Id: I227d078eebee2d92488454707d4dab8ecc24a4d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32958 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-18libpayload: define cbtable tags as enum to identify conflictsPatrick Georgi
We had a value that was overloaded thrice. By moving them in a common structure and ordering them by value such issues are hopefully avoided in the future. Change-Id: I0c7762601d7620413989b458fa634d7606accc9d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32957 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14libpayload/i8042/keyboard: Log errors during initializationFurquan Shaikh
Add error messages for all failed commands in keyboard_init(). Change-Id: Ie42ccbc4d850912c83e00376b27f192d5b652057 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13libpayload: Add USB support to mistral configPatrick Georgi
Change-Id: I2ef42f7d607eec6166d762ad71c0d9540906589d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com>
2019-06-06Revert "libpayload: Reset PS/2 keyboard"Nico Huber
Documentation is scarce on the matter, however the related coreboot code suggests that after the ACK, the keyboard also sends the result of the self test (passed/failed). It looks like this result is never consumed here, probably resulting in further confusion for later com- mands. Let's revert this for now (if it's not too late for the 4.10 release) and break things later again. IMHO, due to the fact that there are dozens of different keyboard controller and keyboard implementations and no accurate specification followed, such changes should be tested on a lot of hardware before merge. This reverts commit a99ed13e3397bc536012120aab8cadb827913863. This reverts commit 7ae606f57f0b3d450ae748141b0e2367041b27d3. Change-Id: I4d4304d5d8a01e013feac61016c59bcaeea81140 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Kepplinger <martink@posteo.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-04libpayload: Add UART for qcs405Prudhvi Yarlagadda
TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04libpayload/i8042/keyboard: Fix return value check for keyboard_cmdFurquan Shaikh
CB:32951 ("libpayload: Reset PS/2 keyboard") added a call to reset keyboard and check the return value of keyboard_cmd() to compare against I8042_KBCMD_ACK. However, keyboard_cmd() already checks for ACK and returns 1 or 0 based on whether ACK is received. This change fixes the check introduced by CB:32951 to compare against 0 just like the other checks for keyboard_cmd(). Additionally, it adds error messages for all failed commands in keyboard_init() to make the prints consistent in case of failure. BUG=b:134366527 TEST=Verified that logs do not contain "ERROR: Keyboard reset failed" anymore. Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-29libpayload/drivers/i8402/kbd: Fix qemuPatrick Rudolph
Reset keyboard controller to fix qemu make scan codes. Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29payloads/external/Linuxboot: Fix Makefile when not using bashChristian Walter
Adding "SHELL := /bin/bash" to the Makefile makes sure, that we use the bash shell which is needed here. Tested with oh-my-zsh. Change-Id: I71495e15b8f1a495af7d8ab21cc5235feb595e01 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33014 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29payloads/external/iPXE: Add more Kconfig optionsPatrick Rudolph
Add two new options: * Disable the prompt "Press Ctrl+B for the iPXE command line..." Add a boolean that disables the initial 2 second timeout. * Include a script that is executed instead of showing a shell. Allows to add a script that will be included into the iPXE ROM. Tested on Lenovo T500 and PC Engines apu2. Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/20782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-27libpayload: Reset PS/2 keyboardPaul Menzel
Loading a libpayload based payload like coreinfo or FILO from SeaBIOS or GRUB pressing keys does not give the expected results. For example, pressing F1 gives the character 24 translated to scan code 6a. ESC for example 43 (111) in coreinfo loaded from SeaBIOS on QEMU Q35. The problem is not reproducible using the payload directly, that means without SeaBIOS or GRUB. The problem seems to be, that those have already initialized the PS/2 controller and AT keyboard. Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to be reset. That seems to fix the issue, when the keyboard was initialized before. TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary payload. Run qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio press 3 to select the coreinfo payload, and verify that the keys F1 and F2 are working. Same with coreinfo loaded from GRUB on the ASRock E350M1. Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23Renumber cbtable tag MMC_INFOPatrick Georgi
We got another tag in the meantime, so resolve the conflict. Change-Id: I64cb5e02a9bed3d8746b75e451c13a1598341ba1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32954 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23coreboot_tables: pass the early_mmc_wake_hw status to payloadBora Guvendik
Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-16libpayload: make log2 and clz work on signed values internallyPatrick Georgi
Needed to make libpayload build clean with -Wconversion. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: Ie193e39854d2231b6d09a2b0deeeef2873e900ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-15payloads/coreinfo: Remove unused variableJacob Garber
The 'last' variable is unused, and has been for the entire history of this file. Found-by: Clang Static Analyzer Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ic86a6d8d2b47585f901f1e48ae88735534c834ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/32796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-15libpayload: ahci: Prevent memory leaks when failing on initJacob Garber
Free several resources when AHCI initialization fails. Note that it is only safe to free resources when the command engine has stopped, since otherwise they may still be used for DMA. Found-by: Coverity CID 1260719, 1260727, 1261090, 1261098 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I6826d79338b26ff9696ab6ac9eb4c59f734687d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13libpayload/drivers/i8042: Add fallthrough commentJacob Garber
Ctrl-delete does nothing, so it falls through to the default case. Add a comment to make this explicit. Found-by: Coverity Scan #1260878 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13libpayload: classify all keyboardsMatt Delco
Depthcharge uses the keyboard type to help determine whether it can trust the keyboard for security-sensitive confirmations. Currently it trusts anything except usb, but now there's a need to distrust ec-based ps/2 keyboards that are associated with untrusted ECs. To help facilitate this, coreboot needs to report more details about non-usb keyboards, so this change replaces the current instances of unknown with enum values that distinguish uart and gpio from ec-based keyboards. BUG=b:129471321 BRANCH=None TEST=Local compile and flash to systems with trusted and non-trusted ECs. Confirmed that security confirmation can't be performed via keyboard on a system with an untrusted EC but can still be performed on a system with a trusted EC. Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-24payloads/seabios: Update the stable git hash of 1.12.1Martin Kepplinger
The Kconfig file has been updated to show 1.12.1 but this is only what gets displayed for the "stable" option. Fix this by updating the actual git hash for the SeaBIOS 1.12.1 release tag. Fixes: fb83ff1a8b ("Update stable from 1.12.0 to 1.12.1") Change-Id: I76dc0dc8b651df0c6ff6f3c02819a70bab8c04cd Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23linuxboot/Kconfig: Remove symbol name of a `choice`Nico Huber
Kconfig somehow adds spurious booleans for each alternative when the choice itself has a name. That's fixed simply by removing the name. Change-Id: Ic35f0697f1f7bb92c12414c17a8790464b376012 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-04-23payloads/U-Boot: Update to the latest stable 2019.4Arthur Heymans
Change-Id: I4740aa80e3c0faf9b18730390af778abcc92aac3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payload/U-Boot: Fix generating a default config on the master branchArthur Heymans
The name of the default configuration file for x86 coreboot changed. Change-Id: I6544142a70bd3e1e13ee52eccbd5335f8375a4f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payloads/U-Boot: Use a phony target for checking out a revisionArthur Heymans
Change-Id: I5ea4df33545f69c06e4ae2158a1a6c14ead784a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23payloads/U-Boot: Unexport the coreboot_exportsArthur Heymans
Without this U-Boot ends up overwriting the coreboot .config when generating a configfile. Change-Id: I62fc0aa3ede0287ffc96915182a2ed5a4877f29d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-21ipxe: Update stable version from 2017.3 to to 2019.3Martin Roth
Updating iPXE stable from commit id fd6d1f4660: Fri Mar 31 09:08:13 2017 +0300 [thunderx] Use ThunderxConfigProtocol to obtain board configuration to commit id ebf2eaf515: Mar 18 10:24:08 2019 +0000 [intel] Add PCI ID for I219-V and -LM 6 to 9 This brings in 176 new commits Change-Id: Id35fee38e0e61897a623dae35f42fc580e32d3ee Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-17mediatek: Use the 64-bit timerTristan Shieh
GPT4 is a 32-bit timer and the counter of GPT4 will overflow in about 330 seconds (0xffffffff / 13MHz). Timer and delay functions will not work properly if the counter overflows. To fix that we should use the 64-bit timer (GPT6). BUG=b:80501386 BRANCH=none Test=emerge-elm coreboot; emerge-kukui coreboot Change-Id: I9f080e47253a1b1bab4636a45cb86c8666a25302 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-04-15LinuxBoot/targets/linux.mk: refactor kernel compilationMarcello Sylvester Bauer
Refactor the linux kernel compilation. Change-Id: Iea2e2c8a22a91bdd2e3f83cd3058426acec3eaba Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-11libpayload/option table: Don't pad string entries with garbageNico Huber
set_option_with() expects a buffer of the exact size of the option. Change-Id: I21332394f88cf2daa4f733a544627d6d3c6ef26c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11libpayload/storage: Add Apollo Lake AHCI ID to tested controllersNico Huber
Change-Id: Iee244d0cd7d64934fbfc34778a45e21e97646628 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11libpayload: keyboard: Add F11 and F12 supportMatt Delco
The firmware is basically ignoring F11 and F12 without this change. BUG=b:130143385 TEST=local compile and flash to device. Confirmed that press of F11 and F12 keys now generates appropriate keypress events (and the same codes that are already generated by these keys on an external USB keyboard). Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-10libpayload: Deduplicate strtol and strtoullJulius Werner
Our strtol() and strtoull() function contain almost exactly the same code. This is a) bad in general and b) may cause the code to get out of sync, such as it recently happened with CB:32029. This patch changes strtol() to be based on strtoull() so that the main parsing code exists only once, and also adds a strtoll() to round off the library. Also fix the bounds imposed by strtoul() to be based on the actual length of a 'long', not hardcoded to 32-bits (which is not equivalent on all architectures). Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MINJulius Werner
Our current limits.h only provides (U)INT_MAX constants. This patch adds most others expected by POSIX. Since some of these may be different depending on architecture (e.g. 'long' is 32-bit on x86 and 64-bit on arm64), provide a definition that will automatically figure out the right value for the data model the compiler is using (as long as it's using two's complement for signed integers, which I think we can assume these days). Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archsJulius Werner
New compilers are a little more stringent about defining the same prototype more than once, so some of our CONFIG_LP_DEBUG_MALLOC wrappers don't quite work the way they are written anymore. Also, several of the printf()s weren't written 64-bit safe. And let's add some double-evaluation safety while I'm here anyway... and I have no idea why this ever depended on CONFIG_LP_USB, that just seems like a typo. Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/14921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 16:24:28 +0000