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BUG=chrome-os-partner:54563
Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Set CONFIG_GRUB2_EXTRA_MODULES from the Kconfig when building GRUB2.
This causes the specified modules to actually enter the built payload.
Change-Id: I345026af705ba8af77c6c12aba8e1bd4135e519c
Signed-off-by: Benjamin Barenblat <bbaren@google.com>
Reviewed-on: https://review.coreboot.org/15203
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Change-Id: If1c37bf2bb7df35d5e5ec37cefb9bb92a251f93b
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/15206
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Antonello Dettori <dev@dettori.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
add a memory barrier before ringing the doorbell, to ensure
all TRB changes are written to memory.
BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform
Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c21e92
Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/346831
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15111
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Including the SeaBIOS bootorder file seems to be a fairly common desire,
so let's make it easy.
Change-Id: Ib0874dee46215287b09c0b52648072ef3ff06ec5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15076
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Some exceptions (like from calling a NULL function pointer) are easier
to narrow down with a dump of the call stack. Let's take a page out of
ARM32's book and add that feature to ARM64 as well. Also change the
output format to two register columns, to make it easier to fit a whole
exception dump on one screen.
Applying to both coreboot and libpayload and syncing the output format
between both back up.
Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14931
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The libpayload CBFS APIs are pretty old and clunky, primarily because of
the way the cbfs_media struct may or may not be passed in and may be
initialized inside the API calls in a way that cannot be passed back out
again. Due to this, the only real CBFS access function we have always
reads a whole file with all metadata, and everything else has to build
on top of that. This makes certain tasks like reading just a file
attribute very inefficient on non-memory-mapped platforms (because you
always have to map the whole file).
This patch isn't going to fix the world, but will allow a bit more
flexibility by bolting a new API on top which uses a struct cbfs_handle
to represent a found but not yet read file. A cbfs_handle contains a
copy of the cbfs_media needed to read the file, so it can be kept and
passed around to read individual parts of it after the initial lookup.
The existing (non-media) legacy API is retained for backwards
compatibility, as is cbfs_file_get_contents() (which is most likely what
more recent payloads would have used, and also a good convenience
wrapper for the most simple use case), but they are now implemented on
top of the new API.
TEST=Booted Oak, made sure that firmware screens and software sync
worked okay.
Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Extend the serial port description to include the input clock frequency
and a payload specific value.
Without the input frequency it is impossible for the payload to compute
the baud-rate divisor without making an assumption about the frequency.
This breaks down when the UART is able to support multiple input clock
frequencies.
Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device
being used as the console UART. Specify this value as zero when the
UART is not on the PCI bus. Otherwise specify the device using bus,
device and function along with setting the valid bit.
Currently the only payload to consume these new fields is the EDK-II
CorebootPayloadPkg.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing is successful when CorebootPayloadPkg is able to properly
initialize the serial port without using built-in values.
Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14609
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb
Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333304
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If a framebuffer is already configured by coreboot, libpayload's
MMU tables didn't mark its memory DMAable (unlike when libpayload
set up its own framebuffer memory).
BRANCH=none
BUG=chrome-os-partner:52826
TEST=depthcharge's recovery screen is not corrupted anymore on kevin
Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8
Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/341092
Reviewed-on: https://review.coreboot.org/14685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:49249
TEST=Compiles and boots and detect USB storage
BRANCH=none
Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3
Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333311
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds a nyan libpayload config, that should fit all nyan devices.
Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14473
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit 785a31d67e8f34065a2483080e4fd7032c3a8aad
(Makefile.inc: Move payload code to payloads/) breaks the usage of
Linux kernel as payload. The reason for it is that cbfs-files-y is
evaluated before payloads/external/Makefile.inc is sourced and as a
consequence ADDITIONAL_PAYLOAD_CONFIG is empty when it is used for
payload options. That leads to missing command line and initrd for
the kernel which in turn leads to kernel panic when it boots.
To avoid it, move the code which adds payload to cbfs completely to
payloads/extranal/Makefile.inc. This way, ADDITIONAL_PAYLOAD_CONFIG is
set right before the payload itself is added to cbfs-files-y.
I have tested this patch with a Linux kernel as well as with SeaBIOS as
payload on mc_tcu3 and it works. If someone sees impact to other
payloads just let me know.
Change-Id: I7aad352f8b3fc1fdba1875b12648b07eba14e282
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14579
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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error: pointer targets of 'strcmp' differ in signedness
expected 'const char *' but argument is of type
'u8 * {aka unsigned char *}'
Change-Id: Id5cbb6fc2efd7c57abc59b08416047e10461436f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id584cbf02c9d3ecb89fcf2a3190f0a73816954a8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14526
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Memtest86+ was pulling origin/master which will change over time. This
adds a commit-id as a stable version to allow it to be reproducible.
The other secondary payloads, coreinfo and nvramcui, do not need this
because they are part of the coreboot repo and not fetched from an
external source.
Change-Id: I20c516010f76cf03342bd8883d0ee7ac5f8bc7e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14520
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This series of patches attempts to update all of the external payload
makefiles to be as similar as possible.
- Add .git to the git repo URL to show that it's a git repo.
- Use the common checkout, fetch, and clone ($(project dir)) targets
- Add TAG-y and NAME-y variables - just with origin/master for now.
Stable will be added shortly.
- Make sure all phony targets are in .PHONY
Change-Id: If83c100841d5f91a9fab7ac44ba20ec2271c0594
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14152
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Get the absolute pathname for LIBPAYLOAD_PATH
- Update distclean:
--correctly remove .config and .config.old - *.config doesn't match
.config
-- remove obsolete files from cleanup
Change-Id: I6aa51b4ac2b392f786aeb12647be5073e6d02df5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14485
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I89dca25d93a4c94cc51f313397e49ba763948450
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: If845729bc34df646a5628ac2a35acc737fd4701d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14483
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add 'nvramcui' target to make it easier to build and test.
Put both nvramcui & coreinfo targets into .PHONY because they
both exist as directories.
Change-Id: I9cf76785e69f3c8e47fe92f1b1648fd0f7a63c3e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14481
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move time functions and prototypes from libpayload.h to time.h.
In a similar manner to other c libary headers, this change makes
porting existing applications to libpayload easier.
Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14437
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When building libpayload, make the build directory and .config outside
libpayload source directory so it'll not pollute the libpayload source
and cause conflicts with other builds.
Change-Id: Idcfbc7dbe4d52a3559229d8450c3efaafd33b93b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14389
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ie38a358ebd2d040ce32b3eeaeb664c568d4dc51e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14378
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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* use crossgcc to build nvramcui
* build libpayload dependency
Change-Id: Ife3054aeb03b4da0568ad47f96c633460d6c07ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14377
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h.
barrier.h is present for x86, arm, and arm64, but not for mips. This
is generating a build error after enabling USB by default on libpayload.
I believe that this slipped through the buiders due to them not getting
cleaned fully. It was caught in the coverity scan and when setting up
a new build server.
Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14391
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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There is a lot of generic code in the 8250 driver that should
be available for non-8250 systems with serial ports as well.
Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I91d9537e8c78560c944c552255e703fc0e6f1f78
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14349
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Most people use USB keyboards.
Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: https://review.coreboot.org/7540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We already have the ability to add a pxe rom to cbfs, but it needs to be
configured and built separately.
This moves the existing Kconfig options for PXE from device/Kconfig and
the top level Makefile.inc to payloads, and adds the option to download
and build iPXE as part of the coreboot build process.
This configures the serial output of iPXE to match coreboot's serial
port configuration by editing the .h files. iPXE doesn't give any
real build-time method of setting these configuration options.
Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There are more modules in a category than categories. Moving the clock
down leaves more space for the list of modules.
Change-Id: I536dafe32e1abb1995c8a1942d70e0d90b905612
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14255
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since r is a pointer, memset(r, 0, sizeof(r)) would only zero the first
4 (or 8) bytes of the newly allocated struct align_region_t.
An alternative to this patch would be to use calloc, or introduce a new
zalloc (zeroed allocation; a single-element calloc) and use that.
Change-Id: Ic3e3487ce749eeebf6c4836e62b8a305ad766e7e
Found-by: Coverity (ID 1291160)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14244
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This allows to accommodate different platforms' default
configurations, memory configuration is fine tuned later during boot
process.
BUG=chrome-os-partner:51537
BRANCH=none
TEST=none yet, the full stack of patches boots fine on EVB
Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a9a71ade4df8a501043f9ae58463a3135e2a4f
Original-Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332384
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/13914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Copy each config in configs/ to the junit_config, update each,
in turn, and clean up when done. This avoids updating the saved
config files and creating dirty files in git.
- Use 'make olddefconfig' instead of 'yes "" | make oldconfig'
- Update clean target to remove junit_config file
- Update distclean target to remove junit.xml
Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Being able to fetch this list will allow the jenkins builder to securely
fetch the external payloads so we can start testing payload builds.
Change-Id: I777229216b2f11f0f427cd5f8cfa003da4171a77
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Instead of adding each payload to each common target, create a list
and loop through the list for all of the payloads
- '.phony' doesn't work - the target needs to be uppercase '.PHONY'
Change-Id: I4a7712c94d0f127c2fff8cb8fada4b8132a4ab3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These makefiles are not included by anything, so they shouldn't be
named Makefile.inc. Also, having them all be named 'Makefile' makes
some other consolidation work I'm doing much easier.
Change-Id: I1234539ba6a0a6f47d2eb0c21de3da3607c6b8de
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14130
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When using coreinfo on a serial console (at least
with gtkterm, picocom and minicom on Ubuntu 15.10)
you can't send F keys to the payload. Allow 1..9
for F1..F9
Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14065
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add all the default options with:
for i in configs/*
do
cp $i .config
make savedefconfig
mv defconfig $i
done
This also switches to minimal config files instead of the full
configuration files that were previously checked in.
Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
LIBCONFIG_PATH -> LIBPAYLOAD_PATH
LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ
Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14099
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
When using PDcurses over a serial line, the background of
coreinfo is not properly cleared. Hence use tinycurses, which
was the only option when coreinfo was developed.
Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14067
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
For CHROMEOS builds, depthcharge can be built automatically.
This dependency exists because depthcharge without vboot and subsequent
signing of the image doesn't work very well, and both are keyed to that
flag as well.
Change-Id: Id0195bd3b4e454f382782106d6512469106daac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/10924
Tested-by: build bot (Jenkins)
|
|
This will allow more payloads to use the standard linker script
instead of implementing their own.
Change-Id: Ie60120769829f427ceb722109d85859b61dbde31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10),
so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised
that this ever worked.
Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14076
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Instead of 500, print 0x00000500 in the ram dump module.
Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14072
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
MEMMAP_RAM_ONLY is not an architecture specific option,
hence move it out of the architecture specific menu.
Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This is adding complexity to the code more than it saves
space, plus some of the tables could potentially be interesting
outside of the ChromeOS context.
Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Bring defconfig and defconfig-tinycurses in sync, so that
defconfig and defconfig-tinycurses only differ in the selection
of the curses implementation.
Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14069
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Since libpayload's LAR support was dropped in If6e36569cd, this module
doesn't compile anymore.
Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14037
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Add an option to specify a git revision from which to build SeaBIOS.
Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13937
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
|
|
- Change the makefile command $(shell pwd) to $(CURDIR) to find the
current directory without going out to the shell.
Change-Id: I4890eba6129630acd2883b92de77308d39949443
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13967
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Libpayload installs into the libpayload/ directory under the directory
you point it to. Since we were pointing it to build/libpayload, it
was installing to build/libpayload/libpayload.
Change-Id: I11029fcfb232d9b66eb3f310fa9e663236d4b213
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13966
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
With this patch the numbers are the "base" addresses for the lines,
which is consistent with the PCI configuration space view.
Change-Id: I2c70d976f6f9f9f615d13bc7a634d6f8037e0c7b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14028
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
... instead of the overall first one.
Change-Id: If9b2674ff2ef83b7c24a3388316b6f4128bc1007
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14027
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
An alternative to this patch is to copy the filetypes table from
util/cbfstool/cbfs.h and use that.
Change-Id: Iebf3a7a8912761ff6825a6f51c8b68df0dcc5990
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14026
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I7222544757587b37e0cf632aa01d042414dde223
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14025
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
On emulation/qemu-i440fx, I get this layout:
Name Offset Type Size
cbfs master header 0x0 cbfs header 32
fallback/romstage 0x80 stage 14284
fallback/ramstage 0x38c0 stage 42382
fallback/payload 0xdec0 payload 1165052
config 0x12a600 raw 352
revision 0x12a7c0 raw 572
cmos_layout.bin 0x12aa40 cmos_layout 772
fallback/dsdt.aml 0x12ad80 raw 4000
img/coreinfo 0x12bd80 payload 1165052
(empty) 0x2484c0 null 1799192
bootblock 0x3ff900 bootblock 1456
... which coreinfo displays in the following way, without this patch:
cbfs master header
fallback/romstage
fallback/ramstage
fallback/payload
config
revision
cmos_layout.bin
fallback/dsdt.aml
img/coreinfo
<free space>
Change-Id: I21eb1dfbe52921843d28683c9396e9b27caa4fbf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
- Rename obj to coreinfo_obj so it doesn't conflict with the obj
variable in libpayload.
Change-Id: I2ffb06a87e30a5eeff5b0dfc0ba62b5e9ab46e26
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I3e719e105c4bacd5e02e055d3f00650a1e126656
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13965
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Currently, if SeaBIOS is set as the payload, it gets rebuilt every
single time we do a build.
Change it to re-build just when there’s a config change.
Change-Id: Ib141f2cbf8796d449172432bb30fa4806cf90328
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13948
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This doesn't do anything more than the clean target, but having both
clean and distclean targets in all makefiles makes standardizing the
cleaning routines easier.
Change-Id: I41578de371a8f767ee23266c30e65e928f0985c4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
Previously the SeaBIOS directory would never get updated after the
initial clone because the tag would always match. This can be shown
by noticing that the text 'Fetching new commits from the SeaBIOS
git repo' is never seen.
This change will always try to pull the latest code if 'Master'
is selected.
Change-Id: I460e2fb0c6f683a0f85343d164880c2d9e6d95cc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13947
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fix up commit 4f66648c (payloads/seabios: Upgrade stable from 1.9.0 to
1.9.1), forgetting to update the version number displayed in the Kconfig
menu, by updating the string to 1.9.1.
Change-Id: Idb395d0ea65bcf91c7c9645fd76d428936e91587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14010
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
|
|
To keep the list of 'secondary' payloads from cluttering the payloads
menu, move them into their own menu under the payloads menu. Then they
don't need any dependencies other than the architecture.
Change-Id: I95119750c6ef627ef0de9b5f5cbad085a51ac2bb
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13941
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Move payload clean targets into payloads/Makefile.inc
Add clean targets for coreinfo, nvramcui, Memtest86+
Change-Id: I70c13582311dfba3e309805053159f8a039cb109
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13940
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
SeaBIOS 1.9.1 was released on February 15th, 2016 [1][2] with the changes
below.
```
$ git log --oneline --reverse rel-1.9.0..rel-1.9.1
3403ac4 build: fix typo in buildversion.py
fe4154e xhci: Check for device disconnects during USB2 reset polling
c016236 xhci: Wait for port enable even for USB3 devices
0240428 sdcard: Only enable error_irq_enable for bits defined in SDHCI v1 spec
fe8d986 sdcard: fix typo causing 32bit write to 16bit block_size field
e902d3f nmi: Don't try to switch onto extra stack in NMI handler
dc6498e scsi: Do not call printf() from scsi_is_ready()
6027043 coreboot: Check for unaligned cbfs header
73f00bc fw/pci: do not automatically allocate IO region for PCIe bridges
b3ef39f biostables: Support SMBIOS 2.6+ UUID format
```
[1] http://www.seabios.org/Releases#SeaBIOS_1.9.1
[2] http://seabios.org/pipermail/seabios/2016-February/010493.html
Change-Id: I4bc8224c2a80cbcce54621e941a9c3a92ca04215
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13933
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
This allows memtest86+ to be added to CBFS as a 'secondary'
payload on x86 systems, to be loaded by the main payload
if desired.
Selecting this option, which defaults to no, builds the memtest86+
payload and adds it to CBFS as `img/memtest` which can then be
loaded by for example SeaBIOS or GRUB.
Change-Id: Iecf876aaf588ba1df7abdf6668cb26f089bf5f42
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13858
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
|
|
Without this change it'll get a build error with crossgcc-x64
because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32",
and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of
"x86_64-elf-as".
Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13845
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This allows coreinfo to be added to CBFS as a 'secondary'
payload on x86 systems, to be loaded by the main payload
if desired.
Selecting this option, which defaults to no, builds the coreinfo
payload and adds it to CBFS as `img/coreinfo` which can then be
loaded by for example SeaBIOS or GRUB.
Change-Id: I52661d486823bc4bb215ce92dca118c9d2c2a309
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13728
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Users had to build nvramcui manually because payload.sh was only meant
for abuild. Now the user can build it with:
cd payloads/libpayload/ && make menuconfig && make && make install
cd ../nvramcui && make
Change-Id: I409a3c39a1e1738e8071febb1a3f169e1aee959a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/13778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
When U-Boot isn't selected as a payload, two of the targets:
$(project_dir): and $(project_dir)/$(TAG-y) evaluated to the same
value, generating a make warning when running a clean. By adding
additional text to the file that is created, this is avoided.
Gets rid of these warnings:
Makefile.inc:54: warning: overriding commands for target `u-boot'
Makefile.inc:37: warning: ignoring old commands for target `u-boot'
Change-Id: I4b4df753612b674b3ccde2a757338840be92d1f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This patch ports the LZ4 decompression code that debuted in libpayload
last year to coreboot for use in CBFS stages (upgrading the base
algorithm to LZ4's dev branch to access the new in-place decompression
checks). This is especially useful for pre-RAM stages in constrained
SRAM-based systems, which previously could not be compressed due to
the size requirements of the LZMA scratchpad and bounce buffer. The
LZ4 algorithm offers a very lean decompressor function and in-place
decompression support to achieve roughly the same boot speed gains
(trading compression ratio for decompression time) with nearly no
memory overhead.
For now we only activate it for the stages that had previously not been
compressed at all on non-XIP (read: non-x86) boards. In the future we
may also consider replacing LZMA completely for certain boards, since
which algorithm wins out on boot speed depends on board-specific
parameters (architecture, processor speed, SPI transfer rate, etc.).
BRANCH=None
BUG=None
TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on
Oak to be about ~20ms faster (cutting load times for affected stages
almost in half).
Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13638
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13671
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
|
|
- Add Kconfig and Makefile options to use U-Boot as a payload.
- Add Kconfig option for extra cbfstool command line arguments.
- Add Kconfig & Makefile option to load the payload as a flat binary.
- Add u-boot directory to .gitignore.
This is currently working for X-86 only.
Graphics worked in U-Boot correctly by initializing the VBIOS and
setting up a console mode.
Tested in QEMU and on Minnowboard Max. Got into U-Boot, have not
booted an OS yet.
Change-Id: Ia122a4ad7cd7d96107c1552b0376c8106ca8fb92
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/12714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I3004eac248561b0cd4e44bcef90fc66fae5d77ca
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13727
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
|
|
SeaBIOS only supports standard IO based serial ports. If the serial
port being used by coreboot isn't a standard IO serial port, disable
the serial console in the SeaBIOS build.
Change-Id: I386b46625fca0bd0a5416ed9831f8370c294ed74
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13617
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This fixes serial on rk3288.
Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13636
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
|
Move the payloads section of the kconfig tree out of the top level
kconfig file and into a separate Kconfig just for payloads before
it starts to get added to.
Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13608
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Add timer driver for armada38x
BUG=chrome-os-partner:47462
TEST=emerge-cyclone libpayload
BRANCH=tot
Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635
Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313343
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13114
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a single target to do the full coreinfo build using default Kconfig
values for both coreinfo and libpayload.
Change-Id: Id622fb2df480e826f6d868dbe01385d76587be26
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13426
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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config and revision data need to be around before they're added to CBFS.
Change-Id: I195156773effd5137c3fda3639c002fbec6e7158
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12971
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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cbgfx_init can fail for multiple reasons. These codes help debugging
cbgfx_init.
BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados
Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b
Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315550
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12930
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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These files need to be added to cbfs-files after PAYLOAD_CONFIG
and PAYLOAD_VERSION have been defined. Where they were before,
they didn't get added to the final build.
Change-Id: Ib1b230f9eb72a8c1710ef473a9f24c0fb7ec6e17
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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archive.h is a header file for the programs which need to parse an archive
created by 'archive' tool. See archive.h for the format description.
BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados
Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311201
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/12734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)
Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12654
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)
Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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SeaBIOS dropped support of VERSION variable and
is reproducible without it.
Change-Id: Iea1dc20e18aa5c274060e3cd55cd9e95086a602d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12645
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
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Make sure the build system knows how to start building the various
integrated payloads we support.
Change-Id: I2128d09c78795e0a41b055975e9f7052e3d951ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12641
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We don't need COREBOOT_ROM_DEPENDENCIES anymore because the dependencies
are taken care of by the cbfs-files mechanism. REFCODE_BLOB also doesn't
need to be an explicit dependency.
Change-Id: I3f32cce79683e57a174724179bc2ac59a8cdda94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12648
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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SeaBIOS updated how versioning is done, and out/version.c no longer
exists. The new file with version information is autoversion.h.
Change-Id: I10abee73ecc51e52c9ff7a2e7a9099339b1a4b40
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12567
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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* The default boot menu key is now the ESC key (instead of F12)
* Initial support for Trusted Platform Module (TPM) hardware and BIOS calls
* Initial support for chain loading SeaBIOS from Grub (via multiboot
support)
* Initial support for booting from SD cards on real hardware
* virtio 1.0 device support
* The build will no longer include the build hostname or build time on
"clean" builds. This makes the build binaries more "reproducible".
* Basic support for running SeaBIOS on Baytrail Chromebooks
* SeaVGABIOS improvements:
* Improved support for old versions of x86emu (the "leal"
instruction is now emulated)
* Several bug fixes and code cleanups
Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12566
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This has been replaced by the PAYLOAD_CONFIGFILE option, allowing
any SeaBIOS config option to be set by a platform.
Change-Id: I584c4c481266740840158baba76581d68e69b448
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12570
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Instead of adding various SeaBIOS options into the coreboot Kconfig,
just add a way to use saved SeaBIOS .config files. These files
can contain full SeaBIOS .configs, but is really intended for individual
options.
The coreboot Kconfig options take precedence over the settings in the
saved .config.
Change-Id: Ia7f9c76555b8e290777207b3f637c94c4d67a782
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12568
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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This change revives the path which was made inert by CL:308520. When
media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer
to a default media. Thus, get_cbfs_range does not set cbfs offset &
size from lib_sysinfo.
BUG=chrome-os-partner:47772
BRANCH=tot
TEST=Tested on Jerry and Glados
Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89
Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313205
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross
compiler toolchain.
Restrict to x86_32 gcc compiler.
Tested in QEMU
Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12454
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12577
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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The more generic 8250 driver can handle both port-mapped and memory-
mapped 8250-compatible UARTs, with different register sizes. Thus, a
separate driver for MMIO32 is not needed.
The generic 8250 driver was tested to work for both output and input,
on Apollolake SoC, which only presents an MMIO32 UART.
Change-Id: Idab766588ddd097649a37de92394b0078ecc660a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12524
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The old bootlog_module implementation was completely broken:
- It assumed that the console buffer is located at address 0x90000,
and of size 64K. It is not correct nowadays.
- It displayed the buffer in a very hacky way, the code was riddled with
TODOs and FIXMEs. Scrolling had sometimes unexpected behavior.
The new implementation:
- Uses the cbmem console as the source of data.
It takes the console information from lib_sysinfo of libpayload, which is
constructed from the coreboot tables (no more hardcoded adressess).
- Properly sanitizes the console buffer for display, which makes
scolling and display much easier to implement.
Change-Id: I3f87ec920631da2acfd3f52273228703f22f469f
Signed-off-by: Yasha Cherikovsky <yasha.che3@gmail.com>
Reviewed-on: http://review.coreboot.org/12440
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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