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2020-08-19arch/arm: Enable FIT payloadsSam Lewis
Implements fit_payload_arch for the arm (aarch32) architecture, so that FIT images can be used. The implementation is very similar to the existing implementations for arm64 and riscv, and has mostly been lifted from these other ports. TEST: Booted Beaglebone Black (in progress port, to be submitted soon!) with a FIT image containing a 5.4 kernel, dtb and initramfs. Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233 Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-18payloads/nvramcui: Fix `make clean`Nico Huber
After `make clean` a new build should not be based on stale artifacts. Hence we have to remove them. Change-Id: I540a83a6c87b843b1c4c9c55990bf3e91fe90d79 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18payloads/coreinfo: Fix `make clean`Nico Huber
After `make clean` a new build should not be based on stale artifacts. Hence we have to remove them. Change-Id: I18292c674986078d991668124193b6aa31234d47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17payloads/seabios: Update stable version to 1.14.0Elyes HAOUAS
see https://seabios.org/Releases Change-Id: I20e57314b867581f41921178ff1ffcbaa50a0843 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-17libpayload/defconfig: Set default heap size to 1MiBNico Huber
libpayload's drivers keep growing. With certain hardware/payload combinations (last time witnessed with Kontron/bSL6 and FILO), the default configuration runs out of memory. As there is a lot enabled by default, also set a big default heap size. Tested with FILO on QEMU/Q35. Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-13libpayload: cbgfx: Add color mapping functionalityYu-Ping Wu
Similar to set_blend(), add set_color_map() for mapping background and foreground colors of a bitmap. Also add clear_color_map() for clearing the saved color mappings. Note that when drawing a bitmap, the color mapping will be applied before blending. Also remove unnecessary initialization for static variable 'blend'. BRANCH=puff BUG=b:146399181, b:162357639 TEST=emerge-puff libpayload Change-Id: I640ff3e8455cd4aaa5a41d03a0183dff282648a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-28libpayload: Replace include/compiler.h with commonlib/bsd's versionPatrick Georgi
This ensures that it's available under BSD license terms. Change-Id: Ica13014b847473fee02516be0b27684c6cfb07bc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25payloads/libpayload/drivers/usb/usb.c: Remove whitespace before tabElyes HAOUAS
Change-Id: Iba73ae4d89cef94f238e9a74300f6088669f355b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/libpayload/curses/menu/eti.h: Remove unneeded whitespacesElyes HAOUAS
Change-Id: Ia77c5be4b22740f88fb9c11bff95036adbd8145f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/libpayload/arch/arm/cpu.S: Remove whitespaces before tabElyes HAOUAS
Change-Id: I2960f95937db23aa3a38ca64085728e6d10968f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25payloads/external/tint/Makefile: Remove whitespaces before tabElyes HAOUAS
Change-Id: Ie08e92778e029b962cf0ed5f95ab740458e82fc5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23libpayload: cbgfx: Add draw_line()Yu-Ping Wu
Add a function draw_line() to draw either a horizontal or vertical line segment. Theoretically a horizontal line can also be drawn by calling draw_rounded_box() with dim_rel.x being the line length and dim_rel.y being the line width. However, due to the truncation in integer division when converting relative coordinates to absolute ones, this will potentially produce inconsistent line widths, depending on the value of pos_rel.y. It is guaranteed that draw_line() will produce consistent line widths, regardless of the position of the line. Also, when the thickness argument is zero, this function is able to draw a line with 1-pixel width, which is not achievable by draw_rounded_box(). BRANCH=puff BUG=b:146399181, b:161424726 TEST=emerge-puff libpayload Change-Id: I2d50414c4bfed343516197da9bb50791c89ba4c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-07-21libpayload/xhci: Try harder to read 32-bit caps at onceNico Huber
With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI register issue) we restructured our capability register accesses because the compiler used the wrong access size. While we do use only 32-bit types now, a compiler may still try to be clever and optimize things in unexpected ways. So we add an explicit read32() now. For instance for the 8-bit MaxPorts field, in the most significant bits of `capreg + 4`, our read + mask + shift ((cap)->hciparams1 & 0xff000000) >> 24 was turned into a single 8-bit read instruction by GCC on x86: 31: 0f b6 52 07 movzbl 0x7(%edx),%edx Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-16libpayload: allow nonblocking delay and more than one delayRonald G Minnich
Extend the local APIC timer delay so that it can be started, and waited for, independently. Add an EOI so that more than one APIC timer interrupt is possible. Previous to this, because there was no EOI, the first timer interrupt the CPU took was also the last it would take -- apic_delay would only work one time. Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-15cbgfx: Add blend functions to calculate transparencyShelley Chen
Up until now we have no way of adding transparency into our firmware screens. Add set_blend() and clear_blend() functions to store alpha value and rgb values to calculate alpha blending in calculate_colors(). BUG=b:144969091,b:160839199 BRANCH=puff TEST=dut-control power_state:rec press ctrl-d Ensure background is dimmed when dialog pops up Change-Id: I95468f27836d34ab80392727d726a69c09dc168e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-15payloads/depthcharge: Makefile: resolve fail of concurrent buildMichael Niewöhner
Resolve missing dependency to fix concurrent building. Resolves: https://ticket.coreboot.org/issues/271 Change-Id: Idbd9155e01fcc4571a61f1bba5b2b4a446036da0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-12payloads/external: fix depthcharge build from sourceSelma BENSAID
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: I17ae7450a9641268fe392bed0f24846abc8e6f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43203 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12payloads/tianocore: Don't recurse submodulesBenjamin Doron
Upstream does not require it. From the repository readme: "Note: When cloning submodule repos, '--recursive' option is not recommended. EDK II itself will not use any code/feature from submodules in above submodules. So using '--recursive' adds a dependency on being able to reach servers we do not actually want any code from, as well as needlessly downloading code we will not use." Change-Id: I0c5d6dd6e5070720870fc22b2476c6fe8dc7fd40 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-09libpayload: cbgfx: Replace bilinear resampling with LanczosJulius Werner
This patch improves the image resampling (scaling) code in CBGFX to use the Lanczos algorithm that is widely considered the "best" resampling algorithm (e.g. also the first choice in Python's PIL library). It is of course much more elaborate and therefore slower than bilinear resampling, but a lot of the difference can be made up with optimizations, and the resulting code was found to still produce acceptable speeds for existing Chrome OS UI use cases (on an Arm Cortex-A55 device, time to scale an image to 1101x593 went from ~88ms to ~275ms, a little over 3x slowdown). Nevertheless, if this should be too slow for anyone there's also an option to tune it down a little, but still much better than bilinear (same operation was ~170ms with this). Example images (scaled up by a factor of 7): Old (bilinear): https://i.imgur.com/ytr2n4Z.png New (Lanczos a=3): https://i.imgur.com/f0vKluM.png Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-09libpayload: Add simple 32.32 fixed-point math APIJulius Werner
struct fraction is slooooooooooow. This patch adds a simple 64-bit (32-bits integral, 32-bits fractional) fixed-point math API that is *much* faster (observed roughly 5x speed-up) when doing intensive graphics operations. It is optimized for speed over accuracy so some operations may lose a bit more precision than expected, but overall it's still plenty of bits for most use cases. Also includes support for basic trigonometric functions with a small lookup table. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id0f9c23980e36ce0ac0b7c5cd0bc66153bca1fd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-08libpayload: arm64: silence libpayload main entryMichael Walle
No other architecture in libpayload outputs anything in the main entry routine. Let alone an exception test which looks like a real exception to the normal user and is most likely really misleading. Silence the startup code. Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866 Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43126 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08libpayload: arm64: fix OUTPUT_ARCH()Michael Walle
There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With this change libpayload will build with the AArch64 GCC. Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1 Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-06libpayload: cbgfx: Fix add_fractions() overflow reductionJulius Werner
log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code would not shift. That's a bad idea, though, since 0xffffffff when interpreted as an int32_t would become a negative number. We need to always shift one more than the current code does to get a safe reduction. This also means we can get rid of another compare/branch since -1 is the smallest result log2() can return, so the shift can no longer go negative now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-28libpayload/cbgfx: Fix overflow in transform_vector()Yu-Ping Wu
Fix potential overflow when multiplying integers in transform_vector(). This issue is causing the absolute coordinate of the bottom right corner of the box to be incorrectly calculated for draw_rounded_box(), which is used in menu UI to clear the previous screen. In addition, check the lower bound in within_box(). BRANCH=none BUG=b:146399181, b:159772149 TEST=emerge-puff libpayload TEST=Previous screen is cleared properly for menu UI Change-Id: I57845f54e18e5bdbd0d774209ee9632cb860b0c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22libpayload: gdb: Condition video console init on LP_VIDEO_CONSOLEYu-Ping Wu
With the stub video_console_init() removed from depthcharge in CL:2241493, depthcharge will fail to compile: payloads/libpayload/gdb/stub.c:76: undefined reference to `video_console_init' Since video_console_init() is meant to be implemented in libpayload, libpayload should be consistent with itself by not calling this function when it's not implemented (i.e., when !LP_VIDEO_CONSOLE). Therefore, initialize video console only if LP_VIDEO_CONSOLE is set. BRANCH=none BUG=none TEST=USE="menu_ui" emerge-gale depthcharge Change-Id: Ic45f9073330258cb77301003484ec525b2404180 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42505 Reviewed-by: Joel Kitching <kitching@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06payloads/external: s/PROMT/PROMPT/gAngel Pons
Change-Id: Id305d9edecac9e9cd305301e9dc5af6678ef7528 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-06usb/xhci: Fix timeout logicCaveh Jalali
This fixes a logic bug in how timeouts are reported back. In the timeout case, the original code would return -1 instead of 0. All call sites expect a return value of 0 as the timeout indicator. Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I81a888aa0a1544e55e6a680be8f3b7f6e0d87812 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-06libpayload: drivers/usb: add a USB pre-poll hookCaveh Jalali
This adds a hook so that a payload can optionally perform USB service functions in conjunction with regular USB port status polling. In particular, this allows depthcharge to control the state of an external USB mux. Some SoCs like Tiger Lake have a USB mux for Type-C ports that must be kept in sync with the state of the port as reported by the TCPC. This can be achieved by hooking into the poll routine to refresh the state of the USB mux. BUG=b:149883933 TEST=booted into recovery from Type-C flash drive on volteer Change-Id: Ic6c23756f64b891b3c5683cd650c605b8630b0fb Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-28payloads/libpayload/libc: Avoid NULL pointer dereferenceHarshit Sharma
Avoid dereferencing a NULL pointer in case of function parameter 'ptr'. Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Change-Id: I5dba27d9757fb55476f3d5848f0ed26ae9494bee Reviewed-on: https://review.coreboot.org/c/coreboot/+/41698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-28payloads/libpayload/libc: Do cosmetic fixesHarshit Sharma
Make the code follow the coding style. Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Change-Id: I4ca168c4aedddef51103b270f105feab93739ecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/41649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-26libpayload/cbgfx: Remove gap between adjacent boxesYu-Ping Wu
When drawing two adjacent boxes with draw_box(), there will be a gap between them. This is due to the truncation in integer division when calculating the bottom right coordinate of the box. In this patch, the relative bottom right coordinate is calculated before transforming to an absolute one. The same issue is also fixed for draw_rounded_box(). Also check validity of 'pos_rel' and 'dim_rel' arguments for draw_rounded_box(). BRANCH=none BUG=chromium:1082593 TEST=emerge-nami libpayload Change-Id: I073cf8ec6eb3952a0dcb417b4c3c3c7047567837 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-18libpayload: Fix definitions of minimum integer valuesYu-Ping Wu
Fix incorrectly defined constants INT16_MIN, INT32_MIN and INT64_MIN, which recursively call themselves. BRANCH=none BUG=none TEST=emerge-nami libpayload Change-Id: I1fa8402d318393de2e02f1e632ab78b6ec0768e8 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41391 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09payloads: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: I9f74ed19257bc4234465b8f912deff1b485173f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41179 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS MakefileMichał Żygowski
The hardware IRQ option was not passed to SeaBIOS Makefile and resulted in HARDWARE_IRQ being permanently disabled regardless of Kconfig selection in coreboot. On platforms that need the hardware IRQ it caused hangs at boot menu or iPXE prompts. TEST=enter SeaBIOS boot menu on Libretrend LT1000 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iafcfd743177bbcd1ee23e227c74dd8268c4c23c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04libpayload/drivers/usb/xhci: Allow xHCI v1.2 in libpayloadDossym Nurmukhanov
The latest Intel FSP advertises xHCI v1.2 chipset support, so update libpayload to include that version. No critical changes were identified in review of the xHCI v1.2 spec, and booting from USB works with the included change as expected. BUG=b:155315876 TEST=booting from multiple USB sticks/hubs with the latest Intel FSP that advertises xHCI v1.2 Change-Id: I236fed9beef86ff5e1bf7962d882fdae5817a1ff Signed-off-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41039 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04payloads/external/GRUB2: Makefile: fix check for changed files againMichael Niewöhner
This fixes the missing closing brace introduced in CB:40953. Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41036 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04payloads/external/GRUB2: Makefile: fix checkout hintMichael Niewöhner
The git checkout hint introduced in cb:36343 does not get printed but executed instead. Escape the single-quotes to fix this. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I1277c3788a141b25cd9f22ec0476ee56b64aea4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-05-04payloads/external/GRUB2: Makefile: fix check for changed filesMichael Niewöhner
The check for changed files, introduced in cb:36343 does not work (anymore?) due to the quotes. Thus, drop them. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ie126e3d604990b2346f1f004f912080104e2789d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-05-02payloads/seabios: Add Hardware IRQ KconfigMatt DeVillier
Certain boards require SeaBIOS' HARDWARE_IRQ option to be deselected in order for the platform to boot. Add a Kconfig to allow selection of HARDWARE_IRQ enablement, and write to SeaBIOS' .config file in cases where it needs to be disabled. Deselect the option for google/rambi variants so they boot with boards defaults. Test: build/boot google/clapper, verify board boots vs hanging at boot menu prompt. Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02libpayload: xhci: Fix CAPREG address calculationJulius Werner
I rushed CB:40895 in to fix a bug only to introduce another. xhci_init() no longer crashes, but it doesn't correctly initialize the XHCI controller either, and unfortunately the error messages are all hidden behind USB_DEBUG. This patch fixes the incorrect address calculation to what it was before CB:39838. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I14293e2135108db30ba6fd2efea0573fe266fa37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01libpayload: Fix 16-bit read/write to PCI_COMMAND registerElyes HAOUAS
Change-Id: I34facbe0cbbdc91066799b586d96abca1599c509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40743 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01lp/drivers/usb: Add quirk for QEMU XHCI root hubDuncan Laurie
The QEMU XHCI driver does not implement the Port Change Detect bit in the USBSTS register. As a result no devices are attached without looking at each port individually. Detect this as a quirk based on the QEMU XHCI controller PCI ID, and apply it to the root hub quirk list so it can get used by the generic hub driver to skip this check. With this change an attached USB mass storage device is detected and able to boot when supplied to qemu: -drive if=none,id=usbmsc,format=raw,file=/tmp/disk.img -device qemu-xhci,id-xhci -device usb-storage,bus=xhci.0,drive=usbmsc Change-Id: I6689cb1dbb24c93d45f5c5ef040b713925d07588 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39839 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30payloads/tianocore: Fix check for custom bootsplashMatt DeVillier
-n needs to check against a string, but if CONFIG_TIANOCORE_BOOTSPLASH_FILE is unset, then $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) evaluates to nothing and the check fails, leading the Makefile to try and copy a non- existant file/path. Change-Id: Iff717dd48748cff16f485bafaa91c7a225fb5bdb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-30payloads/ipxe: Enable HTTPS supportFelix Singer
Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-04-30libpayload: xhci: Do not memcpy registersJulius Werner
memcpy() is meant to be used on normal memory and often implemented with architecture-specific optimizations to make that as performant as possible. MMIO registers often have special access restrictions that may be incompatible with whatever memcpy() does. For example, on arm64 it uses the LDP (load pair) to load 16 bytes at a time, which makes 4-byte MMIO registers unhappy. This patch removes the caching of the XHCI capreg registers and changes it back to a pointer. The CAP_GET() macro is still accessing a full (non-bitfield) uint32_t at the end so this should still generate a 4-byte access (which was the goal of the original change in CB:39838). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id058c8813087a8e8cb85f570399e07fb8a597108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28payloads/tianocore: Allow custom boot splash for UefiPayloadPkgMatt DeVillier
Allow a custom boot splash to be used with UefiPayloadPkg: - remove Kconfig guards restricting to CorebootPayloadPkg - set destination path for logo file based on bootloader selected Test: build/boot qemu with UefiPayloadPkg with custom boot logo Change-Id: Ia0a10d1528f516f6b9d3645b83be0fb4e85bc348 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28payloads/tianocore: Init submodulesMatt DeVillier
Recent changes to upstream edk2 necessitate ensuring that Tianocore's submodules exist and are up to date, otherwise building UefiPayloadPkg will fail. Change method used to detect a dirty tree so that initialized submodules do not taint the result. Test: build qemu with Tianocore UefiPayloadPkg option successfully. Change-Id: Ie2541f048966ec0666d8196508ccdb6c5f089de6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20libpayload: Make 8250 UART driver relocation safeNico Huber
`lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Accessing the wrong value during relocation of FILO resulted in a hang with DEBUG_SEGMENT and UART console enabled. Work around that by caching the whole table entry locally. An alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reto Buerki <reet@codelabs.ch> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14lp/drivers/usb: Work around QEMU XHCI register issueDuncan Laurie
The QEMU XHCI controller does not support byte/word reads from the capability register and it expects dword reads only. In order to make this work move the access of the capability register fields to use macros instead of a packed struct bitfield. This issue was filed upstream: https://bugs.launchpad.net/qemu/+bug/1693050 The original fix attempt in 2012 was not effective: https://github.com/qemu/qemu/commit/6ee021d41078844df60a3a466e3829a3e82776f3 With this change the controller is detected properly by the libpayload USB drivers. Change-Id: I048ed14921a4c9c0620c10b315b42476b6e5c512 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09payloads/nvramcui: Select USE_OPTION_TABLEMatt DeVillier
nvramcui requires use of CMOS for NVRAM configuration, so depend on HAVE_OPTION_TABLE and select USE_OPTION_TABLE to ensure that nvramcui is actually functional when included in a build. Change-Id: I0595514f636b8ce67bbc789ecc96a93c99068c50 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-03libpayload: malloc: Change memcpy() to memmove() in reallocJulius Werner
Our realloc() works (somewhat suboptimally) by free()ing the existing allocation and then reallocating it wherever it fits. If there was free space before the old location, this means the new allocation may be before the old one, and if the free space block is smaller than the old allocation it may overlap. Thus, we should be moving memmove() instead of memcpy() to move the block over. This is not a problem in practice since all our existing memcpy()s are simple iterate and copy front to back implementations which are safe for overlaps when the destination is in front of the source. but it's still the more correct thing to do (in case we ever change our memcpy()s to do something more advanced or whatever). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I35f77a94b7a72c01364ee7eecb5c3ff5ecde57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-01cros_ec: add chrome EC headers to include pathCaveh Jalali
This adds the path to chrome EC headers to the depthcharge build. Depthcharge currently includes a manually maintained copy of the EC headers which are perpetually out of sync with the real interface definitions. By adding the include path, we can build depthcharge with the actual EC interface definitions and eliminate the manual maintenance of copies of EC headers. Once the include path is in place, we can remove the copies of the EC headers from depthcharge. BUG=b:152373049 Change-Id: I1ce0ad9dc99ea52f177d4fb034fd23efd95a7864 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-03-23libpayload/drivers/nvram: Fix coding stylePatrick Georgi
If one branch has braces all should have them. Change-Id: I94e70c6c6188768d9b37a2d154f4d5b8af31f78c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39396 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23libpayload/drivers/nvram: Add function to write RTCPatrick Rudolph
Add a function to set the RTC to provided struct tm. Change-Id: I17b4c1ee0dcc649738ac6a7400b087d07213eaf0 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10libpayload/corebootfb: Replace obsolete macros FI and CHARSNico Huber
These macros serve no purpose anymore, let's do the substitution manually once and for all. Also update the comment on the macros and fix whitespace on the touched lines. TEST=Checked that there are no changes in compiled code. Change-Id: Ib60f9ab157e2e7d44b551dd4f695a6c25ebeb405 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-09libpayload: Add uart/serial driver support for trogdorT Michael Turney
Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09libpayload: Improve rtc functionsPatrick Rudolph
On Lenovo T500 the RTC readings where wrong, as RTC has different encodings, depending on the statusB register. Support BCD vs binary RTC format and AM/PM vs 24h RTC format. Fixes wrong date and time on Lenovo 500. Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09libpayload/corebootfb: Add option to center a 80x25 consoleNico Huber
This makes payloads which are hardcoded to a 80x25 console look much better, e.g. FILO with its "GRUB" user interface. Change-Id: I9f4752328d85d148cd40a0c2337c7191e1d6a586 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09libpayload/corebootfb: Keep local copy of framebuffer infoNico Huber
Keeping a local copy of the framebuffer info allows us to make changes, e.g. add offsets. It also avoids trouble with relocation. Change-Id: I852c4eb229dd0724114acb302ab2ed7164712b64 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-04libpayload: add read64() and write64()Thomas Heijligen
Change-Id: I6febf13ed54a7707f5a99d3d2715c36e18517c12 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03payloads/ext/Makefile.inc: Fix SeaBIOS race conditionAngel Pons
For a very long time, SeaBIOS sometimes failed to build when using multiple threads. This known problem has been haunting everyone for a very long time. Until now. Unlike most other payloads, building SeaBIOS results in two files: the SeaBIOS payload itself and SeaVGABIOS. Each file has its own target, and there's a third target called "seabios", which has the same recipe as the SeaBIOS file, which calls `payloads/external/SeaBIOS/Makefile` with a bunch of arguments. In addition, SeaVGABIOS depends on "seabios". When executing serially, if the file of either SeaBIOS or SeaVGABIOS is needed, the SeaBIOS Makefile will be run. This will generate both files, so it is not necessary to run the Makefile more than once. However, when using multiple threads, it can happen that one thread wants to make the SeaBIOS file, while another one wants to make the SeaVGABIOS file, which depends on "seabios". This implies that both threads will execute the SeaBIOS Makefile at about the same time, only to collide when performing git operations. Since git uses a lock file when updating the index, one of the threads will fail to acquire the lock with an error, which will ultimately cause the build to fail. Whenever this happened, manually aborting with Ctrl-C made the build process fail again because of the same error. The only way to get past this problem, other than using one thread, was to let the unfinished jobs complete. The thread that acquired the lock on the SeaBIOS git repository would finish building SeaBIOS, so that target would not need to be remade. When restarting the build, only the target that failed is rebuilt, so it does not collide with any other thread. To address this issue, make the SeaVGABIOS file target depend directly on the SeaBIOS file instead, and remove the duplicate "seabios" target. Change-Id: I251190d3bb27052ff474f3cd1a45022dab6fac31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-02lz4: Fix out-of-bounds readsAlex Rebert
Fix two out-of-bounds reads in lz4 decompression: 1) LZ4_decompress_generic could read one byte past the input buffer when decoding variable length literals due to a missing bounds check. This issue was resolved in libpayload, commonlib and cbfstool 2) ulz4fn could read up to 4 bytes past the input buffer when reading a lz4_block_header due to a missing bounds check. This issue was resolved in libpayload and commonlib. Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02libpayload: cbfs: fix infinite loop in cbfs_get_{handle,attr}Alex Rebert
cbfs_get_handle() and cbfs_get_attr() are both looping over elements to find a particular one. Each element header contains the element's length, which is used to compute the next element's offset. Invalid or corrupted CBFS files could lead to infinite loops where the offset would remain constant across iterations, due to 0-length elements or integer overflows in the computation of the next offset. This patch makes both functions more robust by adding a check that ensure offsets are strictly monotonic. Instead of infinite looping, the functions are now printing an ERROR and returning a NULL value. Change-Id: I440e82fa969b8c2aacc5800e7e26450c3b97c74a Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-29payloads/tianocore: Enable PS2 keyboard moduleBenjamin Doron
Upstream UEFIPayload[1] now includes support for PS2 keyboards, but defaults it to disabled. Enable it, as CorebootPayload does. Note that this increases payload size in coreboot by a little over 5 KiB. 1. https://github.com/tianocore/edk2/commit/33a32936510ecff00d0b6aeaeb9c8b2bf5430b8b Change-Id: If6d468809142a0049ce1648217d62b070229ad6b Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38960 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-28payloads/ext/tianocore/Makefile: Enable quiet modeAngel Pons
The build process of this payload is unnecessarily prolix. Therefore, make use of the `-q` flag to abridge the output. TEST=When building for X64, UEFIPAYLOAD.fd does not differ. Change-Id: I6eba069ff5be2813d180dae40ab10155f0542f33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39123 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24libpayload: cbgfx: Fix potential overflowing expressionYu-Ping Wu
BRANCH=none BUG=none TEST=none Change-Id: Icd37a6abc01d9fcbcf54525d47b15c9930a9b9fb Signed-off-by: Yu-Ping Wu <yupingso@google.com> Found-by: Coverity Scan #1419491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24libpayload: Fix out-of-bounds readAlex Rebert
Fix an out-of-bounds read in the LZMA decoder which happens when the src buffer is too small to contain the 13-byte LZMA header. Change-Id: Ie442f82cd1abcf7fa18295e782cccf26a7d30079 Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-22cbfs: allow uncompressed payloadsRonald G. Minnich
Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39051 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17payloads: Fix typosElyes HAOUAS
Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17libpayload/corebootfb: Fix character buffer relocationNico Huber
The `chars` pointer references the heap which is part of the payload and relocated along with it. So calling phys_to_virt() on it was always wrong; and the virt_to_phys() at its initialization was a no-op anyway, when the console was brought up before relocation. While we are at it, add a null-pointer check. Change-Id: Ic03150f0bcd14a6ec6bf514dffe2b9153d5a6d2a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-17libpayload: arm64: Keep instruction cache enabled at all timesJulius Werner
This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-02-05libpayload: Make pci and endian handling -Wconversion safePatrick Georgi
Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-02-05libpayload/xhci: Fix MPS handling in set_addressKangheui Won
We set MPS to speed_to_default_mps(speed) initially but later compare maxpacketsize with 8 to change mps. So compare with speed_to_default_mps(speed) to determine if we need to change settings here. BUG=b:147783572 BRANCH=none TEST=works with 12Mbps/8MPS USB device Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04coreinfo/coreinfo.c: Correct main function signatureJacob Garber
libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14libpayload: cbgfx: Support drawing a box with rounded cornersYu-Ping Wu
A function draw_rounded_box() is added to draw a box with rounded corners. In addition, this function is different from draw_box() in 2 ways: - The position and size arguments are relative to the canvas. - This function supports drawing only the border of a box (linear time complexity when the thickness is fixed). BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie480410d2fd8316462d5ff874999ae2317de04f9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-27Makefile: Remove romccElyes HAOUAS
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-20libpayload/drivers/i8042: add error messages to i8042_probeEric Lai
Print error message before error return for better debugging. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I52039dcab72c6295dfb6b887a7000a6d2bd050ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/37689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-16libpayload: Implement reading from CBMEM consoleYu-Ping Wu
To support showing CBMEM logs on recovery screen, add a function cbmem_console_snapshot() to copy the CBMEM console to an allocated buffer. Non-printable characters are automatically replaced with '?' to ensure the returned string is printable. BRANCH=none BUG=b:146105976 TEST=emerge-nami libpayload Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-13payloads/seabios: Update stable from 1.12.1 to 1.13.0Martin Kepplinger
SeaBIOS 1.13.0 has been tagged on 20191209. Major changes in this release: * Support for reading logical CHS drive information from QEMU * Workaround added for misbehaving optionroms that grab "int19" * The TPM 2 "PCR bank" option can now be set from the TPM menu * SeaVGABIOS support for QEMU "atiext" display * Several bug fixes and code cleanups see http://seabios.org/Releases Change-Id: I37c8a72b0819bc4d19da9f7ab8e90f907e3e4dec Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-13libpayload/drivers/i8042: Add error handlingEric Lai
Add error handling on I8042_CMD_WR_CMD_BYTE failure. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-12libpayload/drivers/i8042: Remove obsolete flagEric Lai
CB:37594 change the flag makes PC_KEYBOARD_IGNORE_INIT_FAILURE obsolete. Remove it. BUG=b:145130110 TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcf816155b32dd691b48a7479297b556d32dd6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11libpayload/drivers/i8042: Add AT translated Keyboard supportEric Lai
Wilco device uses the AT translated keyboard and doesn't need to set scancode set. Remove the ignore flag and put into translation mode instead. BUG=b:145130110 TEST=Draillion keyboard is usable on every boot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-09payloads/bayou: remove unhooked payloadAngel Pons
The bayou payload is not attached to the build system in any way, and has not been for quite a while. Since selecting it in Kconfig does nothing, remove this payload now that coreboot 4.10 has been released. Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06endian: Replace explicit byte swapping with compiler builtinJulius Werner
gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-05arm64: Bump exception stack size to 2KBJulius Werner
To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-05trogdor: libpayload USB supportT Michael Turney
Change-Id: I26c28f9af8d819f4644e383e8d0293a3d5de9eef Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04mmio: Add clrsetbitsXX() API in place of updateX()Julius Werner
This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot tableYu-Ping Wu
Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-28libpayload: Add BIT(x) macro definitionsatya priya
Add BIT(x) macro definition in libpayload. Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40 Signed-off-by: satya priya <skakit@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove imgtec/pistachio SoCJulius Werner
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19mmio: Fix buffer_to_fifo32() order of argumentsJulius Werner
buffer_to_fifo32() is a simple wrapper to buffer_to_fifo32_prefix(), but unfortunately its arguments are swapped. This patch fixes the issue. Change-Id: I6414bf51dd9de681b3b87bbaf4ea4efc815f7ae1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36942 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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