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2014-12-19libpayload: hexdump: Use `p` as conversion specifier for pointersPaul Menzel
Change-Id: Ie5c279ef90bd9ed5e2624bf852dcff1f06531a13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4767 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-19libpayload/libc/hexdump.c: Take `const void *memory` as argumentPaul Menzel
`*memory` is not changed in `hexdump()` and just read so make it `const`. Change-Id: I9504d25ab5c785f05c39c9a4f48c21f68659a829 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5403 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-17libpayload: usb: Detach unused USB devicesShawn Nematbakhsh
If a payload decides not to use a USB device then the device can be detached. This prevents the device from interfering with normal operation on some platforms. Also, it aligns the behavior of usb_generic_init with class-specific init functions such as usb_msc_init, which will detach unsupported devices. BUG=None TEST=Manual on Squawks. Test recovery boot w/ USB 2.0 media, verify that media boots and no babble error is encountered. BRANCH=rambi Change-Id: I8fb30951d273e4144cda214a30a2e86df90f2c1c Original-Change-Id: Iee522344558749603defb2966e18765aa195dae2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195401 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f7778ace68c9bee8dfab2b263e5dd054fc50c3bb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15arm: Fix minor mistake in cache maintenance assemblyJulius Werner
Turns out that when you clear 28 bits starting with bit 3, you leave bit 31 standing. Ooops... This shouldn't really matter since that bit is reserved/SBZ in CLIDR anyway, but it's still nice to fix it. This whole thing should really be an AND for clarity anyway in my opinion. Bug found in upstream NetBSD (who would've thought...). BUG=None TEST=Still boots. Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193300 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-09ARM: API to Map Physical Address to Wipe Memory above 4GBDaisuke Nojiri
TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some chars, then verified they can be read from the pointer returned. BUG=chrome-os-partner:25587 BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88 Original-Reviewed-on: https://chromium-review.googlesource.com/188894 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529 Reviewed-on: http://review.coreboot.org/7658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09libpayload: ARM: Keep track of the CPSR when exceptions happen.Gabe Black
Use the SPSR to extract and inject CPSR values when an exception happens and pass that information to exception hooks. The register structure GDB expects when using its remote protocol has a spot for the CPSR. BUG=None TEST=Built and booted on link, nyan. BRANCH=None Original-Change-Id: Id950fb09d72fb0f81e4eef2489c0849ce5dd8aca Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/180253 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8e7014f24a580f84c91fa7b0369dfa922918adcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I49357fb6a65edeff7a9a48d54254308a6b0efdb7 Reviewed-on: http://review.coreboot.org/7657 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09libpayload: Make it possible to install callbacks for particular exceptions.Gabe Black
To support a GDB stub, it will be necessary to trap various exceptions which will be used to implement breakpoints, single stepping, etc. BUG=None TEST=Built and booted on Link with hooks installed and saw that they triggered when exceptions occurred. Built and booted on nyan. BRANCH=None Original-Change-Id: Iab659365864a3055159a50b8f6e5c44290d3ba2b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/179602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db0897b1ddad600e247cb4df147c757a8187626) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e7f724b99988cd259909dd3bd01166fa52317ec Reviewed-on: http://review.coreboot.org/7656 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09libpayload: arm: Pass the coreboot table location to the payload.Gabe Black
To find the coreboot tables, the payload has historically searched for their signature in a predefined region of memory. This is a little clumsy on x86, but it works because you can assume certain regions are RAM. Also, there are areas which are set aside for the firmware by convention. On x86 there's a forwarding entry which goes in one of those fairly small conventional areas and which points to the CBMEM area at the end of memory. On ARM there aren't areas like that, so we've left out the forwarding entry and gone directly to CBMEM. RAM may not start at the beginning of the address space or go to its end, and that means there isn't really anywhere fixed you can put the coreboot tables. That's meant that libpayload has to be configured on a per board basis to know where to look for CBMEM. Now that we have boards that don't have fixed amounts of memory, the location of the end of RAM isn't fixed even on a per board level which means even that workaround will no longer cut it. This change makes coreboot pass the location of the coreboot tables to libpayload using r0, the first argument register. That means we'll be able to find them no matter where CBMEM is, and we can get rid of the per board search ranges. We can extend this mechanism to x86 as well, but there may be more complications and it's less necessary there. It would be a good thing to do eventually though. BUG=None TEST=Built and booted on nyan. Changed the size of memory and saw that the payload could still find the coreboot tables where before it couldn't. Built for pit, snow, and big. BRANCH=None Original-Change-Id: I7218afd999da1662b0db8172fd8125670ceac471 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185572 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ca88f39c21158b59abe3001f986207a292359cf5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iab14e9502b6ce7a55f0a72e190fa582f89f11a1e Reviewed-on: http://review.coreboot.org/7655 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02Drop tianocoreboot ("Project PIANO")Patrick Georgi
There are four other approaches to provide UEFI on top of coreboot that actually get to a UEFI shell. No need to keep this experiment and confuse users. Change-Id: I81c52e24099852f6daf0d5725aec707bdfd75ae1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7622 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-02tianocoreboot: Update config to make it compileMarcel Meißner
Change-Id: Ie584460529dcd342702dc00787df9c20e2ef10e7 Signed-off-by: Marcel Meißner <mm-meissner@gmx.de> Reviewed-on: http://review.coreboot.org/7541 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
This patch changes the ENTRY() macro in asm.h to create a new section for every assembler function, thus providing dcache_clean/invalidate_all and friends with the same --gc-sections goodness that our C functions have. This requires a few minor changes of moving around data (to make sure it ends up in the right section) and changing some libgcc functions (which apparently need to have two names?), but nothing serious. (You may note that some of our assembly functions have data, sometimes even writable, within the same .text section. This has been this way before and I'm not looking to change it for now, although it's not totally clean. Since we don't enforce read-only sections through paging, it doesn't really hurt.) BUG=None TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not output into any binary anymore since no one actually uses it. Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/183891 (cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9 Reviewed-on: http://review.coreboot.org/7451 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Add minimal support for PL011 UARTMarcelo Povoa
This creates a new PL011 config variable which avoids the infinite busy wait on serial_putchar() because the register mapping is not compatible with current implementation. BUG=None BRANCH=none TEST=printf() works on the PL011 based ARMv8 foundation model Original-Change-Id: I9feda35a50a3488fc504d1561444161e0889deda Original-Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/187020 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 85779a34a161c324cc8af995ada4393137275f20) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: payloads/libpayload/Config.in payloads/libpayload/drivers/serial.c Change-Id: I23c8b3728cd7d2d7692b3e86a679e061e88f7bb5 Reviewed-on: http://review.coreboot.org/7422 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: timer: Move the timer drivers from depthcharge to libpayload.Gabe Black
These drivers are needed right away and never really fit into depthcharge's driver model anyway. CQ-DEPEND=CL:194064 BUG=None TEST=Built and booted nyan, link, and peach_pit and verified that timer values in cbmem were reasonable. Built for nyan_big, nyan_blaze and daisy. BRANCH=None Original-Change-Id: Ia7953cfece57524262a6c7d6537082af7a00f4d6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194058 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit f30a410f0a248c93bc34f5868af1596bf8ce3cdd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I782d20f3cd63210a87c712643c7a53753f5ef301 Reviewed-on: http://review.coreboot.org/7225 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-13libpayload: usb: Remove automatic clear_stall() calls from transfersJulius Werner
We've recently fixed a problem where an external hard drive would choke due to one too many CLEAR_FEATURE(HALT) commands in the XHCI stack with "libpayload: usb: xhci: Fix STALL endpoint handling". Clearing stall conditions from within the transfer function is wrong in general... this is really something that is host controller agnostic and should be left to the higher-level driver to decide. The mass storage driver (the only one that should really encounter stalls right now) already contains the proper amount of clear_stall() calls... any more than that is redundant and as we found out potentially dangerous. This patch removes automatic clear stalls from UHCI and OHCI drivers as well to make things consistent between host controllers. BUG=chromium:192866 TEST=None. I could borrow the original hard drive from Shawn and compile a Snow to only use the OHCI driver to reproduce/verify this, but alas, I am lazy (and it's really not that important). Original-Change-Id: Ie1e4d4d2d70fa4abf8b4dabd33b10d6d4012048a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193732 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit d46e183f3e7e0b0130becdefa6fd3ef8097df54b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie8f4ab3db8ec0d9a2d1e91c62967833e59c46700 Reviewed-on: http://review.coreboot.org/7223 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: usb: Fix up usb_shutdown() code pathsJulius Werner
This patch combines a few minor fixes and refactoring to the various host controller and root hub drivers to ensure they all do the right thing on a call to usb_exit(). It puts a usb_detach_device(0) call into detach_controller() so that the HCD doesn't need to remember to tear down the root hub itself, and makes sure all root hubs properly detach the subtree of devices connected to their ports first (as generic_hub and by extension XHCI had already been doing). It also fixes up some missing free() calls and replaces most 'ptr = malloc(); if (!ptr) fatal()' idioms with the new x(z)alloc(). BUG=chromium:343415 TEST=Tested EHCI on Big and OHCI, EHCI, and XHCI on Snow. Could not test UHCI (unless anyone volunteers to port coreboot to a ZGB? ;) ), but the changes are really tame. Original-Change-Id: I6eca51ff2685d0946fe4267ad7d3ec48ad7fc510 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193731 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5791b546e5a21a360d0c65888a5b92d5f48f8178) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I00138f0aeceb12ed721f7368c7788c9b6bee227d Reviewed-on: http://review.coreboot.org/7222 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Remove config.pantherMarc Jones
config.panther was added in a chromium upstream patch. We don't want mainboard specific configs in libpayload, so remove it. Change-Id: Ibfb894a0262911c13e88bc161749b78e2b5c5185 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7450 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13libpayload: Update defconfigsMarc Jones
Update x86 and ARM defconfig. Adds default N to specific timer and serial drivers. Change-Id: Ida6b953565dc6053729c2a72c6342d86596c599b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7449 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09libpayload: serial: Move the depthcharge serial drivers into libpayload.Gabe Black
These drivers need to be ready right away and never really fit into the depthcharge driver model anyway. CQ-DEPEND=CL:194063 BUG=None TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze, and daisy. BRANCH=None Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194057 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93 Reviewed-on: http://review.coreboot.org/7224 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-09arm: Thumb ALL the things!Julius Werner
This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). BUG=None TEST=Snow and Nyan still boot. Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182212 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Conflicts: payloads/libpayload/include/arm/arch/asm.h src/arch/arm/Makefile.inc src/arch/arm/armv7/Makefile.inc *** There is an issue with what to do with ramstage-S-ccopts, and *** will need to be covered in additional ARM cleanup patches. Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-02SeaBIOS Makefile.inc: Remove build dir for uppermem optionMartin Roth
The build directory got removed while my patch was in flight and I didn't notice when I submitted it. The uppermemory change was added in commit 4d7d25f38a - http://review.coreboot.org/#/c/6364 The output directory was changed for everything else in commit ab11a6a94c - http://review.coreboot.org/#/c/6460 Change-Id: Ib8311f694280d305e826adbb76e3e7b722b30e0f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7298 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-29libpayload: usb: ehci: Honor 10ms reset recovery periodJulius Werner
This patch adds the 10ms TRSTRCY delay between a reset and the following Set Address command that is required by the USB 2.0 specification to the EHCI root hub driver. The generic_hub driver that's used for XHCI and external hubs already included this delay. This is such a glaring violation of the spec that I'm really amazed how many USB 2.0 devices we tested before seemed perfectly fine with responding to a Set Address within 2 microframes of the reset... It also increases the port reset hold delay by one millisecond to avoid an ugly race condition on Tegra SoCs: they decided to time the 50ms themselves instead of relying on the CPU to do it (fair enough), and to automatically transition Port Reset to 0 and Port Enable to 1 after that (bad idea). If the CPU's read-modify-write to clear Port Reset races exactly with the host controller setting Port Enable, we may end up clearing the bit again and going into the companion controller handoff path later on. The added millisecond shouldn't cause any problems for other host controllers and is not a big deal compared to other delays in this code path. BUG=chrome-os-partner:26749 TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always gets detected correctly. Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/189872 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d Reviewed-on: http://review.coreboot.org/7221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22libpayload: usb: Make OHCI work with ARM systemsJulius Werner
This patch enables the OHCI driver to use DMA memory, which is necessary for ARM systems where DMA devices are not cache coherent. I really only need this to test some later OHCI changes, but it was easy enough... copied almost verbatim from ehci.c. Change-Id: Ia717eef28340bd6182a6782e83bfdd0693cf0db1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193730 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit e46b6ebc439e86a00e13bf656d60cf6c186a3777) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7010 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22libpayload: usb: xhci: Fix STALL endpoint handlingShawn Nematbakhsh
- Remove the call to clear_stall in xhci_reset_endpoint because we will call clear_stall from the mass-storage driver. - Remove the xhci_reset_endpoint call from xhci_bulk on STALL since we will reset on the next transfer anyway. - Remove the clear_halt parameter from xhci_bulk since it's now unused. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I852b87621861109e596ec24b78a8f036d796ff14 Reviewed-on: https://chromium-review.googlesource.com/192866 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit e67e4f0545cbdc074328c83c7edccf9e712cd7be) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7011 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-17libpayload: Don't use default path for kconfigNico Huber
libpayload's kconfig is totally incompatible with other kconfig versions, today. Using other versions just doesn't work any more, so don't use the overridable $(obj)/util/kconfig path. Choose a path that reflects the incompatibility: $(obj)/util/lp_kconfig, instead. This whole every-(sub)project-has-it's-own-patched-kconfig-version makes me really, really sad :'-( Change-Id: I964772f3323dc20aa7c1cc26a384a2fbca1dbb5e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-17libpayload: Fix missed CONFIG_ -> CONFIG_LP_ substitutionsNico Huber
Change-Id: I1c64a9a649398ebe2eda179907c470f99caa9fc3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16libpayload: also support armv7-a toolchainPatrick Georgi
Change-Id: I9b80b72de96fb28489dcc8547b8f748ea4fcc355 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7074 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com>
2014-10-04Kconfig: Allow native vga init to be selectable for SeaBIOS payloadEdward O'Callaghan
Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6891 Tested-by: build bot (Jenkins) Reviewed-by: Kevin O'Connor <kevin@koconnor.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-02libpayload: usb: xhci: Treat port reset as a port status changeShawn Nematbakhsh
If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-10-02libpayload: usb: Remove generic roothub reset port functionShawn Nematbakhsh
The generic roothub reset port function is overly broad and does some things which may be undesirable, such as issuing multiple resets to a port if the reset is deemed to have finished too quickly. Remove the generic function and replace it with a controller-specific function, currently only implemented for xhci. Change-Id: Id46f73ea3341d4d01d2b517c6bf687402022d272 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189495 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 54e1da075b0106b0a1f736641fa52c39401d349d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-29libpayload: Build libpayload with debugging info turned up all the way.Gabe Black
Pass -ggdb3 to the compiler when building libpayload, -ggdb so that it uses "the most expressive format available", and 3 so that the debugging level is set to 3, the highest value currently supported. The debugging information can be stripped by the payload consuming the library, and will definitely be stripped by cbfstool when installing that payload into an image. Change-Id: Ifd6c4a928fbb0b9fa9b3b2e0ea298abff31baf3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/180252 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit dc04daaf099c53c57508b66e08f40945345a56ca) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29arm: Fix up new cache flush algorithm and replace dcache_*_all() with itJulius Werner
This patch fixes the remaining few bugs in our shiny new cache iteration by set/way/level algorithm to actually make it work: It makes it start from cache level 0 (previously it would always start at LoC and be "done" instantly), fixes up the two shifts that isolate the set bits at the end (which didn't seem to account for the fact that the first shift affects the second), and throws an S bit on that last shift so that it actually affects the conditionals after it. In addition, also moves the next_level block to the top so that we can share (and thus eliminate) some code at initialization, and turns the whole thing into a thrice-instantiated macro to create functions that fit our existing interface. Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 6d94f8330191c316fe093ddb5288329453da8a4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6932 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-25libpayload: Add missing cache API stub to x86Julius Werner
This patch adds another cache invalidation stub to the x86 arch to make it usable in common code. This whole stuff should probably be redesigned anyway but I just want to get it working and unblock my CL for now... more cleanups coming later. Change-Id: I2e8bdd8aa0e6723209384c24042f053f2e993fe6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182534 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit cafce5182a7a2a9ce17ad40d9d893a40ebd5aafd) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6919 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-22arm: Update mem* functions to newer versionsJulius Werner
The memcpy/memset/memmove assembly implementations have been taken from U-Boot, which originally got them from Linux. I turns out that they are actually not that bad, but they could use an update. This patch pulls in the current Linux upstream versions of those files, removing some old U-Boot cruft such as checking whether the two pointers in a memcpy() are equal (really now?) or side-stepping the R8 register because it was used for special purposes. It also returns to the good old Linux ENTRY/ENDPROC macros since we have them now anyway, and straightens out the W() macro in preparation for unified thumb support. Change-Id: I138af269b423bef0a237759ac29f1ee58ca206a0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182179 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 777127997bde5785b21d422d0b6eb04c4328b478) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6918 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22arm: Move libgcc assembly macros to arch/asm.hJulius Werner
libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22libpayload: Add vboot handoff parsing on ARMStefan Reinauer
This is needed by depthcharge on ARM if coreboot is loading its ramstage from the RW section of the ROM. Change-Id: I96c6c04a0cee39854b45f2eda169e93461da0694 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/176757 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cf26be4cb527b0fc4212d401a8c77ceb1c7992d0) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6906 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-15libpayload: x86: Add support for catching processor exceptions.Gabe Black
This functionality is already available for ARM, so lets add it to x86 as well. We'll want to be able to hook exceptions when running as a remote GDB target. Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179601 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6898 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-15libpayload: Add a timer_us() function.Gabe Black
This function returns the number of microseconds scaled from the number of raw timer ticks. It accepts a base parameter which is subtracted from the current time, which makes it easy to keep track of relative times. Change-Id: I55f2f9e90c0e12cda430bbe88b044f12b0b563c8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179600 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4dd549e18d170dbf918c5b4b11bbe1f4e99b6695) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6897 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-15libpayload: Add wrappers for malloc which check its return value.Gabe Black
The xmalloc wrapper checks whether the malloc succeeded, and if not stops execution and prints a message. xmalloc always returns a valid pointer. The xzalloc wrapper does the same thing, but also zeroes the memory before returning it. Old-Change-Id: I00e7de04a5c368ab3603530b98bd3e3596e10632 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/178001 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4029796d4f66601e33ae3038dbfc3299f56baf89) libpayload: malloc: Fix xmalloc() for zero byte allocations The C standard considers it legal to return a NULL pointer for zero length memory allocations, and our malloc implementation does in fact make use of that. xmalloc() and xzmalloc() should therefore not consider this case a failure. Also fixed a minor formatting issue. Old-Change-Id: Ib9b75df9458ce2ba75fd0bc0af9814a3323298eb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178725 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3033437e9d89c6072464860ea50ea27dcb76fe54) Squashed 2 libpayload malloc related commits. Change-Id: I682ef5f4aad58c93ae2be40e2edc1fd29e5d0438 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6890 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-15libpayload: Add a new "die" function to fatally signal programming errors.Gabe Black
If a programming error is detected, die can be used to print a message and stop execution similar to failing an assert. There's also a "die_if" function which is conditional. die functions, like asserts, should be used to trap programming errors and not when the hardware does something wrong. If all code was written perfectly, no die function would ever be called. In other words, it would be appropriate to use die if a function was called with a value that was out of bounds or if malloc failed. It wouldn't be appropriate if an external device doesn't respond. In the future, the die family of functions might print a stack trace or show other debugging info. Old-Change-Id: I653fc8cb0b4e459522f1b86f7fac280836d57916 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/178000 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 59df109d56a0f5346562de9b3124666a4443adf0) libpayload: Fix the license in some files which were accidentally made GPL. Some files were accidentally made GPL when they were added to libpayload. This change changes them over to a BSD license to be in line with the intended license of libpayload. Old-Change-Id: Ia95ac4951b173dcb93cb489705680e7313df3c92 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/182202 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f47600e50e82de226f2fa6ea81d4a3d1c56277b) Squashed the initial patch for "die" functions and a later update to the license header. Change-Id: I3a62cd820e676f4458e61808733d81edd3d76e87 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6889 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-14payloads/external/SeaBIOS: Bump version to 1.7.5Edward O'Callaghan
Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6900 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-13arm: Put exception_stack into BSSJulius Werner
"Hey guys, I have this awesome idea! How about we put a huge array filled with 0xa5 into the data segment of our uncompressed romstage for no particular reason? Give our SPI driver something to do so it doesn't get too bored, you know?" Guess it pays off to just hexdump our image and sanity-check it top to bottom every once in a while... Also reduces the size because 8K is crazy just to print a bunch of registers (256 bytes ought to be enough for anybody). Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176762 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c) arm: Remove exception_test() The exception_test() mechanism might have been useful when exceptions were first implemented, but now that they are pretty stable it's really not necessary anymore (especially not on every single boot in production Chromebooks). It forces a simple unaligned access, and as we start having exceptions in stages that might not have paging turned on yet, it's better to remove that completely. Also removed the duplicated implementations of SCTLR-stuff and switched to the existing ones in cache.h. Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177101 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9) Squashed 2 exception related commits. Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-12payloads/external/SeaBIOS: Allow setting buffers below 0xC0000Martin Roth
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12arm: Remove some pointless CFLAGSJulius Werner
This patch removes the -ffixed-r8 CFLAG from the coreboot and libpayload Makefiles. This seems to be a relic from U-Boot, which uses that register to keep it's global data structure pointer. There's no reason for us to throw away a perfectly fine register on this already pretty constrained architecture. Also removed a config.h inclusion from the Makefile because that should really be done inside the C files. Change-Id: Ia176c0f323c1be07cddf88fa5488788786a27cdf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177110 Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a81112abde284ba09020db6afa363169911a7f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6880 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10libpayload: usbhid: Fix typo on descriptor parsingJulius Werner
Forgot an asterisk and everything goes to hell. Sorry about that. Change-Id: I6b2503ca3ea0f80d4e4e5d8b8c0e986fec5db2c9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173587 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: David James <davidjames@chromium.org> (cherry picked from commit 2a357560a697b56cc6022a4dd3dda47b33568d83) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10libpayload: ehci: Fix byte count in dump_td()Julius Werner
The dump_td() debug function in the EHCI stack incorrectly masks the amount of transferred bytes on output... the actual field is 15 bits wide (30:16). Let's just use the mask constant we already have for all the other code. Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174986 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 570077da7f16bbe2204b4a80790e4bd8fe1a2bd7) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-09-04build: add what-jenkins-does targetPatrick Georgi
This target does (pretty much) exactly the same what jenkins is doing on our build nodes: - complete abuild run of our tree with a given payload - building all libpayload configs we ship - building the cbmem utility In fact at some point we could tell jenkins to just run this command. For debugging, pass along V and Q variables so inner make processes are slightly more noisy on demand. Change-Id: Ib515170603a151cc3c3b10c743f1468a9875dbdc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6797 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-04libpayload: usb: Refactor USB enumeration to fix SuperSpeed devicesJulius Werner
This patch represents a major overhaul of the USB enumeration code in order to make it cleaner and much more robust to weird or malicious devices. The main improvement is that it correctly parses the USB descriptors even if there are unknown descriptors interspersed within, which is perfectly legal and in particular present on all SuperSpeed devices (due to the SuperSpeed Endpoint Companion Descriptor). In addition, it gets rid of the really whacky and special cased get_descriptor() function, which would read every descriptor twice whether it made sense or not. The new code makes the callers allocate descriptor memory and only read stuff twice when it's really necessary (i.e. the device and configuration descriptors). Finally, it also moves some more responsibilities into the controller-specific set_address() function in order to make sure things are initialized at the same stage for all controllers. In the new model it initializes the device entry (which zeroes the endpoint array), sets up endpoint 0 (including MPS), sets the device address and finally returns the whole usbdev_t structure with that address correctly set. Note that this should make SuperSpeed devices work, but SuperSpeed hubs are a wholly different story and would require a custom hub driver (since the hub descriptor and port status formats are different for USB 3.0 ports, and the whole issue about the same hub showing up as two different devices on two different ports might present additional challenges). The stack currently just issues a warning and refuses to initialize this part of the hub, which means that 3.0 devices connected through a 3.0 hub may not work correctly. Change-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170666 Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit ecec80e062f7efe32a9a17479dcf8cb678a4a98b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6780 Tested-by: build bot (Jenkins)
2014-09-04libpayload: usb: Unify USB speed between XHCI stack and USB coreJulius Werner
This patch removes the confusing concept of a special "xhci_speed" with a different numeric value from the usual speed used throughout the USB core (except for the places directly interacting with the xHC, which are explicitly marked). It also moves the MPS0 decoding function into the core and moves some definitions around in preparation of later changes that will make the stack SuperSpeed-ready. It makes both set_address implementations share a constant for the specification-defined SetAddress() recovery delay and removes pointless additional delays from the non-XHCI version. Change-Id: I422379d05d4a502b12dae183504e5231add5466a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170664 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit f160d4439c0d7cea1d2e6b97207935d61dcbb2f2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-31libpayload: xhci: Ensure to reset dequeue pointer on stopped endpointsJulius Werner
This patch fixes a bug in the XHCI stack that occurs when a multi-TRB TD times out before the last TRB is processed. The driver will correctly issue a Stop Endpoint command in that case, but the xHC will still preserve the transfer state and just pick up right after that on the next doorbell ring. It will then process the leftover TRBs from the old TD the next time a transfer is issued. (cf. XHCI 4.6.9) We fix this by changing the existing xhci_reset_endpoint() calls in transfer functions to not only trigger on Halted (2) and Error (4), but also on Stopped (3). That function will not actually issue a Reset Endpoint command in this case, but it will nuke the whole transfer ring and issue a Set TR Dequeue Pointer command, which is sufficient (though slightly overkill) to solve our problem. Change-Id: I3abbe30ff9d4911a8af1f792324e018d427019e8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170833 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit f12424af0e29ac12963e8e5a7970fadcc0bb6cee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6787 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-29arm: libpayload: Make cache invalidation take pointers instead of integersJulius Werner
This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLEGabe Black
While the 8250 compatible serial port driver is primarily useful on x86 systems because it works with the legacy x86 com ports, some devices which aren't x86 based have 8250 compatible UARTs as well. This change renames the CONFIG_X86_SERIAL_CONSOLE option to the more general and direct CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86 systems can enable the driver, although it will default to on on x86 and off otherwise. Also, the default IO port address that's added to the sysinfo structure on x86 and which is intended to be overwritten by a value in the coreboot tables is not used on ARM. That variable is adjusted so that it's more clear it's a default value, and made dependent on x86 since that's the only place its value is actually used. Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170834 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6655 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-28libpayload: usb: Allow direct instantiation of MMIO host controllersJulius Werner
The existing USB_MEMORY mechanism to instantiate non-PCI host controllers is clunky and inflexible... most importantly, it doesn't allow multiple host controllers of the same kind. This patch replaces it with a function that allows payloads to directly instantiate as many host controllers of whatever type they need. Change-Id: Ic21d2016a4ef92c67fa420bdc0f0d8a6508b69e5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169454 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit b6e95c39dd91f654f0a345f17b3196f56adf4891) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-27libpayload: Add ARM defconfigPatrick Georgi
make junit.xml tries to build it, but fails (ARM port doesn't seem to be ready?) Useful test case to demonstrate a failing libpayload build. Change-Id: Iba4fe551b48f631e6a3bd90eb07930fc70761332 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4552 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-19libpayload: usb: Fix several minor USB stack bugsJulius Werner
This patch fixes the following minor bugs in the USB stack: 1. Ensure that all dynamically allocated device structures are cleaned on detachment, and that the device address is correctly released again. 2. Make sure MSC and HID drivers notice missing endpoints and actually detach the device in that case (to prevent it from being used). 3. Make sure XHCI-specific set_address() cleans up all data structures on failure. 4. Fix broken Slot ID range check that prevented XHCI devices from being correctly cleaned up. Change-Id: I7b2b9c8cd6c5e93cb19abcf01425bcd85d2e1f22 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170665 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 9671472263ddd0c30400ae3b6da780a18cd21ded) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6701 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18libpayload: usbmsc: Remove DETACHED state from MSC device structureJulius Werner
The USB MSC device structure contains a "ready" state that can be either "ready", "not ready" or "detached". The last one can only be assigned when the device is completely unresponsive and gets forcefully logically detached via usb_detach_device(). This call (at least in the current version) also calls all destructors and frees the complete usbdev_t structure (including the MSC specific part), which unfortunately makes storing the "detached" state in that very structure a little pointless. This patch reduces the "ready" value to a simple boolean and makes sure that all detachment cases immediately return from the MSC driver, carefully avoiding any use-after-free opportunities. Change-Id: Iff1c0849f9ce7c95d399bb9a1a0a94469951194d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170667 (cherry picked from commit fd4529f37fdd1c93a8b902488ffeef7001b1a05a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6654 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-16libpayload: add march flag for armv7Isaac Christensen
The cache functions for armv7 require 'march=armv7-a' to use the 'isb' and 'dsb' instructions. Change-Id: I3b7ad8fc7da8c3167b38fd1a325090fe49e4ca42 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-16libpayload: change cb_range to lb_rangeIsaac Christensen
Patch 'coreboot_tables: reduce redundant data structures' (1f5487a) added a new lb_range structure to coreboot and libpayload but the original chromium patch added cb_range to libpayload instead. A followup patch 'arm: libpayload: Add cache coherent DMA memory definition and management' (b8fad3d) used the incorrect cb_range structure but this wasn't caught since the current verification build doesn't build libpayload for arm. Change-Id: I7cedc66a4794bf4daa214f54be6e917f96418ff6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6665 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14libpayload: dma_malloc: Prevent warm reboot problems and add debuggingJulius Werner
Since the DMA memory is allocated by Coreboot (outside of the payload's linker script), it won't get zeroed upon loading like the heap. Therefore, a warm reboot that doesn't reset memory may leave stale malloc cookies lying around and misinterpret them as memory that is still in use on the next boot. After several boots this may fill up the whole DMA memory and lead to OOM conditions. Therefore, this patch explicitly wipes the first cookie in init_dma_memory() to prevent that from happening. It also expands the existing memory allocator debugging code to cover the DMA parts, which was very helpful in identifying this particular problem. Change-Id: I6e2083c286ff8ec865b22dd922c39c456944b451 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169455 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8e5e1784638563b865553125cd5dab1d36a5d2cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6645 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14libpayload: xhci: Make XHCI stack usable on ARMJulius Werner
This patch updates the libpayload XHCI stack to run on ARM CPUs (tested with the DWC3 controller on an Exynos5420). Firstly, it adds support for 64-byte Slot/Endpoint Context sizes. Since the existing context handling code represented the whole device context as a C struct (whose size has to be known at compile time), it was necessary to refactor the input and device context structures to consist of pointers to the actual contexts instead. Secondly, it moves all data structures that the xHC accesses through DMA to cache-coherent memory. With a similar rationale as in the ARM patches for EHCI, using explicit cache maintenance functions to correctly handle the actual transfer buffers in all cases is presumably impossible. Instead this patch also chooses to create a DMA bounce buffer in the XHCI stack where transfer buffers which are not already cache-coherent will be copied to/from. Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169453 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14libpayload: Make EHCI driver cache-awareJulius Werner
This patch makes the EHCI driver work on ARM platforms which usually do not support automatic cache snooping. It uses the new DMA memory mechanism (which needs to be correctly set up in the Coreboot mainboard code) to allocate all EHCI-internal communication structures in cache-coherent memory, and cleans/invalidates the externally supplied transfer buffers in Bulk and Control functions with explicit calls as necessary. Old-Change-Id: Ie8a62545d905b7a4fdd2a56b9405774be69779e5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167339 (cherry picked from commit 322338934add36a5372ffe7d2a45e61a4fdd4a54) libpayload: ehci: Cache management is hard, let's go copying... It turns out that my previous commit to make the EHCI stack cache aware on ARM devices wasn't quite correct, and the problem is actually much trickier than I thought. After having some fun with more weird transfer problems that appear/disappear based on stack alignment, this is my current worst-case threat model that any cache managing implementation would need to handle correctly: Some upper layer calls ehci_bulk() with a transfer buffer on its stack. Due to stack alignment, it happens to start just at the top of a cache line, so up to 64 - 4 bytes of ehci_bulk's stack will share that line. ehci_bulk() calls dcache_clean() and initializes the USB transfer. Between that point and the call to dcache_invalidate() at the end of ehci_bulk(), any access to the stack variables in that cache line (even a speculative prefetch) will refetch the line into the cache. Afterwards any other access to a random memory location that just happens to get aliased to the same cache line may evict it again, causing the processor to write out stale data to the transfer buffer and possibly overwrite data that has already been received over USB. In short, any dcache_clean/dcache_invalidate-based implementation that preserves correctness while allowing any arbitrary (non cache-aligned) memory location as a transfer buffer is presumed to be impossible. Instead, this patch causes all transfer data to be copied to/from a cache-coherent bounce buffer. It will still transfer directly if the supplied buffer is already cache-coherent, which can be used by callers to optimize their transfers (and is true by default on x86). Old-Change-Id: I112908410bdbc8ca028d44f2f5d388c529f8057f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169231 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 702dc50f1d56fe206442079fa443437f4336daed) Squashed the initial commit and a follow up fix. Change-Id: Idf7e5aa855b4f0221f82fa380a76049f273e4c88 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-14libpayload: Add in a missing "static".Gabe Black
The readwrite_chunk was private to the usb mass storage driver, but wasn't marked as static which was upsetting the compiler. Change-Id: I0ef5c5f96a29f793dd43ff672a939902bad13c45 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169816 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8140e6145b3d072b7f12a924418570022207c065) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6648 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14payloads/external/SeaBIOS: move build directoryIdwer Vollering
Move SeaBIOS' build directory out of build/ This allows the user to delete build/ in the top dir and keep the built binary in payloads/external/SeaBIOS/seabios/out/ Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-14libpayload: Reduce media init timeout to 5 seconds.Shawn Nematbakhsh
Currently, we wait for up to 30 seconds for a device to become ready to respond to a TEST_UNIT_READY command. In practice, all media devices become ready much sooner. But, certain devices do not function with libpayload's USB driver, and always timeout. To provide a better user experience when booting with such devices, reduce the timeout to 5 seconds. Change-Id: Icceab99fa266cdf441847627087eaa5de9b88ecc Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169209 (cherry picked from commit 9e55204e92adca0476d273565683f211d6803e7a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6647 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14libpayload: Increase accuracy of timeout period for media init.Shawn Nematbakhsh
When bringing up media, we claim to wait for up to 30 seconds for a device to respond to our TEST_UNIT_READY command. Actually, we can wait far longer because we do not take into account execution delay. To improve timeout accuracy, make use of gettimeofday(), which calculates time based upon a CPU counter. This improves the user experience slightly when certain non-working USB devices are used. Change-Id: Id9605ecfc0a522d7a0b039fd8eac541232605082 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169208 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 1d3d535db83ff478c512e37f37015b43927b3efc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-14libpayload: usbmsc: Split transfers into 64KB chunksDuncan Laurie
Add a new function to split transfer requests into chunks of 64KB in order to be as compatible as possible with devices that choke when sent large transfer requests. Change-Id: Id11990bd149af14af5535de4af47bda21d1ab51e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169170 Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 4c413b007aa23da830877127dd556c4c38b43042) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6636 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13arm: libpayload: Add cache coherent DMA memory definition and managementJulius Werner
This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12libpayload: usbhub: Don't clear PSC unless it was setJulius Werner
The current USB hub code always clears the port status change after checking it, regardless of whether it was set in the first place. Since this check runs on every poll, it might create a race condition where the port status changes right between the GET_PORT_STATUS and the CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag before it was ever read. Let's add one extra if() to avoid that possible headache. Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168098 (cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6617 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.Julius Werner
The EHCI host controllers in Samsung Exynos SoC seem to be a little more picky than Intel ones. When they reach the dummy_qh in the periodic frame list, they try to access the next qTD pointer even though it's NULL, and run into a HostSystemError. This patch explicitly sets the Terminate bit on those pointers to mark them invalid. Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66884 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12libpayload: Make USB transfer functions return amount of bytesJulius Werner
The USB bulk and control transfer functions in libpayload currently always return 0 for success and 1 for all errors. This is sufficient for current use cases (essentially just mass storage), but other classes (like certain Ethernet adapters) need to be able to tell if a transfer reached the intended amount of bytes, or if it fell short. This patch slightly changes that USB API to return -1 on errors, and the amount of transferred bytes on successes. All drivers in the current libpayload mainline are modified to conform to the new error detection model. Any third party users of this API will need to adapt their if (...<controller>->bulk/control(...)) checks to if (...<controller>->bulk/control(...) < 0) as well. The host controller drivers for OHCI and EHCI correctly implement the new behavior. UHCI and the XHCI stub just comply with the new API by returning 0 or -1, but do not actually count the returned bytes. Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48308 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Updated the patch to support XHCI as well. Change-Id: Ic2ea2810c5edb992cbe185bc9711d2f8f557cae6 (cherry picked from commit e39e2d84762a3804653d950a228ed2269c651458) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6390 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-11libpayload: xhci: Use Event Data TRBs for transfer event generationJulius Werner
The current XHCI code only sets IOC on the last TRB of a TD, and doesn't set ISP anywhere. On my Synopsys DesignWare3 controller, this won't generate an event at all when we have a short transfer that is not on the last TRB of a TD, resulting in event ring desync and everyone having a bad time. However, just setting ISP on other TRBs doesn't really make for a nice solution: we then need to do ugly special casing to fish out the spurious second transfer event you get for short packets, and we still need a way to figure out how many bytes were transferred. Since the Short Packet transfer event only reports untransferred bytes for the current TRB, we would have to manually walk the rest of the unprocessed TRB chain and add up the bytes. Check out U-Boot and the Linux kernel to see how complicated this looks in practice. Now what if we had a way to just tell the HC "I want an event at exactly *this* point in the TD, I want it to have the right completion code for the whole TD, and to contain the exact number of bytes written"? Enter the Event Data TRB: this little gizmo really does pretty much exactly what any sane XHCI driver would want, and I have no idea why it isn't used more often. It solves both the short packet event generation and counting the transferred bytes without requiring any special magic in software. Change-Id: Idab412d61edf30655ec69c80066bfffd80290403 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170980 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Kees Cook <keescook@chromium.org> (cherry picked from commit e512c8bcaa5b8e05cae3b9d04cd4947298de999d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6516 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10LZMA: Add a version of ulzma which takes the input and output buffer sizes.Gabe Black
This new version is used to implement the version which doesn't take the input and output buffer sizes. Old-Change-Id: I8935024aca0849bc939263d7fc3036c586e63c68 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65510 Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 465d167ad2f6a67d0b2c91fb6c68c8f9a09dd395) libpayload: Make lzma truncation non-fatal. If the size the lzma header claims it needs is bigger than the space we have, print a message and continue rather than erroring out. Apparently the encoder is lazy sometimes and just puts a large value there regardless of what the actual size is. This was the original intention for this code, but an outdated version of the patch ended up being submitted. Old-Change-Id: Ibcf7ac0fd4b65ce85377421a4ee67b82d92d29d3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66235 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 30c628eeada274fc8b94f8f69f9df4f33cbfc773) Squashed two related commits and updated the commit message to be more clear. Change-Id: I484b5c1e3809781033d146609a35a9e5e666c8ed Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6408 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10cbfs: Fix overwalk on file scanSteven Sherk
A bootblock overwalk was occuring when deriving the actual length, the bootblock size was not taken into account and bootblock size was not aligned. Resolved merge conflict. Change-Id: I7eb42f8deaaf223dcf07b37bb7dde4643acd508f Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Steve Sherk <ssherk70@gmail.com> Tested-by: Steve Sherk <ssherk70@gmail.com> (cherry picked from commit 20b0ba479b01755fbdc7f3dd9214e8af923402ba) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6539 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10coreboot_tables: reduce redundant data structuresJulius Werner
There are three coreboot table tags that all define some kind of memory region, and each has their own homologous struct. I'm about to add a fourth so I'll just clean this up and turn it into a generic struct lb_range instead. Change-Id: Id148b2737d442e0636d2c05e74efa1fdf844a0d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167154 (cherry picked from commit 22d82ffa3f5500fbc1b785e343add25e61f4f194) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6456 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10armv7: Support stack dump after exceptionsJulius Werner
This patch enhances the armv7 exception handlers in Coreboot and libpayload to show the correct SP and LR registers from the aborted context, and also dump a part of the current stack. Since we cannot access the banked registers of SVC mode from a different exception mode, it changes Coreboot (and its payloads) to run in System mode instead. As both modes can execute all privileged instructions, this should not have any noticeable effect on firmware operation (please correct me if I'm wrong!). Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6538 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10libpayload: hexdump.c: Change type of length argument to size_tPaul Menzel
Representing a (non-negative) length with a signed integer is not optimal, so change its type to `size_t`. Change-Id: Ic0c2b7e081ba32d917409568ee53007d9ab7f8f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10serial: Separate the serial hardware init and the serial console init.Gabe Black
You might want to use the serial hardware for something other than a console, or you might want to intercede in the serial stream to wrap it in another protocol. This is what you'd do to send output to GDB while using it to debug the payload. Change-Id: I2218c0dbb988dacb64e5bdaf5d92138828eff8b6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179559 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit da9ab46d974745125fe7d8b29ce43336c3586cd5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6547 Tested-by: build bot (Jenkins)
2014-08-09Set check-lxdialog.sh mode properlyVadim Bendebury
This script is used by 'make menuconfig', but being non executable it fails to run, causing the make invocation failure. Setting 'x' mode bits fixes the problem. Change-Id: I925ca4ee056937b6c38ad34f5520fd621f9d9eb0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173564 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 3ddb9d221ecc3df968853d765b566cf0648a7525) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6540 Tested-by: build bot (Jenkins)
2014-08-05libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.Gabe Black
When libpayload header files are included in the payload itself, it's possible that the payloads config settings will conflict with the ones in libpayload. It's also possible for the libpayload config settings to conflict with the payloads. To avoid that, the libpayload config settings have _LP_ (for libpayload) added to them. The symbols themselves as defined in the Config.in files are still the same, but the prefix added to them is now CONFIG_LP_ instead of just CONFIG_. Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65303 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6427 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-01armv7: add wrapper for DCCSW (data cache clean by set/way)David Hendricks
This adds a wrapper for data cache clean (without invalidate) by set/way. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2 Reviewed-on: https://gerrit.chromium.org/gerrit/66118 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001) armv7: clean but do not invalidate caches between stages This cleans the caches without invalidating them between stages. The dcache content should still be valid when the next stage begins, so we should see a small performance gain. (thanks to gabeblack for pointing this out) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa Reviewed-on: https://gerrit.chromium.org/gerrit/66119 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d) armv7: Make coreboot and libpayload cache files the same This merges the difference between the ARM version of cache.c and cache.h for libpayload and coreboot. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93 Reviewed-on: https://gerrit.chromium.org/gerrit/66120 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6) ARM: Fix cache cleaning operation. There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it silently did nothing. Since we started using that to clean the cache between stages and I have a change that enables caches earlier on, this was preventing booting on pit. Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66234 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f) libpayload: Fix data cache cleaning on ARM. A similar fix was made to coreboot where OP_DCCSW was silently not doing anything in dcache_op_set_way. Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66236 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5) Squashed five related commits. Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6418 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Use coreboot’s serial console settingsMartin Roth
Set up the serial console on SeaBIOS to match coreboot's settings. Previously, we were just forcing it on, and setting it to 0x3f8. Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31payloads/external/SeaBIOS: Update makefile for olddefconfigMartin Roth
Instead of creating the SeaBIOS .config file for QEMU, then changing things to be coreboot specific, create a default config for coreboot, then run olddefconfig to use the SeaBIOS defaults as they're set for coreboot. This leads to a cleaner config. Note that CONFIG_THREAD_OPTIONROMS defaults to enabled for SeaBIOS if we're building for coreboot, so I reversed the logic. I *ASSUMED* that leaving CONFIG_QEMU_HARDWARE=y and CONFIG_DEBUG_IO=y previously was an oversight. If this is not correct, please let me know and I'll add them it back in. SeaBIOS disables these by default if building for coreboot. Change-Id: I42c6a56205bb15c6693a5f3a716b7876a4d78abe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6362 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31libpayload: provide missing cbfs symbolAaron Durbin
The generic cbfs code relies on the libpayload_init_default_cbfs_media symbol. However, none was provided for ARM. Provide an empty implementation that returns an error as there is no generic way to locate the default cbfs media. Old-Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56805 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit d3410c28ef9f37b832e2fa2d18351dda332bc9f7) libpayload: place dummy_media.c in correct object list The commit introducing dummy_media.c was placed in the libc object list. This wasn't correct. It should be in the libcbfs object list as well as guarded by CONFIG_CBFS. Old-Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56925 (cherry picked from commit 7937c7c5e95a934593bc0cedd5f4496b4770c303) Squashed two related commits. Change-Id: I84cd132b44cc2ea5b29acf109a3562baaeede9c6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6411 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12mainboard: Add new board Google PantherMohammed Habibulla
(Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer) BUG=chrome-os-partner:23563 TEST=emerge-panther chromeos-coreboot-panther [pg: Drop configs/, which is chromeos stuff, adapted libpayload's config.panther to work with upstream] [pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options] [pm: rebase to master branch of coreboot upstream] [md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set] Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/174555 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Mohammed Habibulla <moch@chromium.org> Tested-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: http://review.coreboot.org/5990 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Drop obsolete setting of reg_base in [oex]hciNico Huber
Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6251 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Catch null-pointer dereference in xHCINico Huber
Fix a possible null-pointer dereference (hopefully) before anyone runs into this. Also don't switch ports to xHCI if initialization failed. Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6245 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: xHCI: Always initialize controller->pcidevNico Huber
As the controller structure is never fully cleared, this one wasn't initialized for non-pci controllers (but checked for non-null later). Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6246 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Use unsigned long for BARs in *hci_init()Nico Huber
Using void* for physical addresses leads to much casting and confuses developers when to convert from physical to virtual addresses or the other way around. When using plain integers for physical addresses and pointers for virtual addresses things become much cleaner and we won't ever end up dereferencing a physical address. Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6244 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10libpayload: Keep physical addresses in console driversNico Huber
Like done in FILO, libpayload's console drivers might be initialized before a relocation. So keep physical pointers in there which won't break on relocation. Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6247 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-10libpayload: Remove redundant phys_to_virt() from xHCI driverNico Huber
Remove a redundant phys_to_virt() that sneaked in the initialization of PCI xHCI controllers. The use of casts from void* to u32 (and vice versa) prompts for things going wrong here. That will be addressed in a later commit. Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/6243 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-28payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4Paul Menzel
SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other things, supports writing debug messages to CBMEM console. The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the SeaBIOS configuration file `.config` as otherwise the SeaBIOS build from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is detected as a new option. This option was already added and enabled in commit 7c1a49bc [1] SeaBIOS: have coreboot pass the choice to run optionroms in parallel so SeaBIOS messages are now written to the CBMEM console. Successfully tested on the Asus M2V-MX SE. [1] http://seabios.org/Releases [2] http://review.coreboot.org/5443 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5093 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23payloads/coreinfo/multiboot_module.c: Trivial fix indentsEdward O'Callaghan
Stylistic fix-up's. Change-Id: I0cad7c860280d0d8dcb16d052846c72f690e2b65 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5731 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-17libpayload: Fix to properly disable serial consoleKyösti Mälkki
With coreboot builds with serial console disabled, there is no CB_TAG_SERIAL entry in coreboot tables. We ended up with lib_sysinfo.serial == NULL and serial_hardware_is_present == 1. Change-Id: I9a2fc0b55bf77769f2f2bfbb2b5476bee8083f7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5723 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09payloads: make build system integration work againPatrick Georgi
Payloads using Kconfig get confused by coreboot Kconfig configuration in environment variables. Prune them. Change-Id: I63da2af0a15dca35d70cd65b2f74a1564aab9483 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5710 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-09payloads/coreinfo/README: Use `It is` instead of `Its`Paul Menzel
Change-Id: Ic1a9f2f01c26ee97cd7183fcf1755cb916f1b02e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5704 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.Edward O'Callaghan
Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16filo payload: Fix the buildPatrick Georgi
Also strip down the config that's set since these are actually SeaBIOS options, not FILO... Change-Id: I5dbe6255996f9e115699ff2a83fb3450533520ee Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4647 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>