summaryrefslogtreecommitdiff
path: root/payloads
AgeCommit message (Collapse)Author
2018-04-27libpayload/include/queue.h: Remove trailing whitespaceElyes HAOUAS
Change-Id: I7ff676f51958e12c40a82f56e68a776ddf429228 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27payloads/coreinfo/README: Remove trailing whitespaceElyes HAOUAS
Change-Id: I467376bab942eac1b6f1f8544bdd96202335b75d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27payloads/external/tianocore: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ibb15d370beb8ba34f24bd86eed19de38a3df3561 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27libpayload/curses/form: Remove trailing whitespaceElyes HAOUAS
Change-Id: I231ea26e8d8bfc53da22a440451802b425c996b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27payloads/libpayload/curses/menu: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ia4bd5224a77914e0561fa35a18aec8db16bff320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-26payloads/depthcharge: Update stable version to upstream masterDuncan Laurie
From commit id 61cfcc3b: eowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2 To commit id 902681db: zoombini: Enable NVMe as boot source Change-Id: Iab7676dd642c13f58dde85940ac1c8b52bfce3b7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-19libpayload: Move GDB functions to stdlib.hJulius Werner
When GDB support is compiled in, halt() in libpayload will call gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in <libpayload.h>. Usually files just include <libpayload.h> so this is not a problem, but in some situatons a payload may just include <stdlib.h> (or a file including it like <assert.h>), leading to an undeclared identifier here. Move the GDB functions to <stdlib.h> to solve this. Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17Use git HTTP URLs without `/p` in itPaul Menzel
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25545 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23arch/arm64/armv8/mmu: Add support for 48bit VAPatrick Rudolph
The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-22payloads/seabios: Update stable from 1.11.0 to 1.11.1Paul Menzel
SeaBIOS 1.11.1 was released with the changes below. ``` $ git log --oneline rel-1.11.0..rel-1.11.1 0551a4b paravirt: Only enable sercon in NOGRAPHIC mode if no other console specified a7aa43e pci: fix 'io hints' capability for RedHat PCI bridges 0e739f2 shadow: Don't invoke a shutdown on reboot unless in a reboot loop 5d9a515 build: Use git describe --always ``` Change-Id: Ia77e98edcd42b28677de9670ce13c2ea5d327315 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/25284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-02-20payloads/external/GRUB2: Build only for supported architecturesJonathan Neuschäfer
GRUB2 doesn't support all architectures that coreboot supports. Furthermore, coreboot's build script for GRUB2 doesn't support all of these architectures. Let the user select GRUB2 only when building for x86 and ARM, which are known to work. Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-16libpayload: usbhid: Zero-initialize all parts of usbhid instance structJulius Werner
The USBHID driver zero-initializes some but not all of the fields in its usbhid_inst_t structure. This is a problem because under some circumstances, some of the uninitialized fields may be read and lead to incorrect behavior. Some (broken) USB keyboards keep sending reports that contain all zeroes even when they have no new keys... these usually get silently ignored, but if the usbhid_inst_t structure is in an inconsistent state where 'previous' is zeroed out but 'lastkeypress' is non-zero because it wasn't properly initialized, these reports will be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch changes the code to just xzalloc() the whole structure so we won't have to worry about initialization issues anymore. Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-15tianocore: fix Makefile to build a custom revision or branchGergely Kiss
Kconfig variables TIANOCORE_REVISION and TIANOCORE_REVISION_ID do not have an effect without this fix, the build process would checkout the hard-coded stable hash even if these variables are set. Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/22983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-10payloads: Add an option to compress secondary payloadsArthur Heymans
Both GRUB and SeaBIOS can chainload lzma compressed payloads. Therefore it is beneficial to compress secondary payloads like Memtest86+, coreinfo, nvramcui,... for both size reasons and often also speed reasons since the limiting factor is generally the IO of the boot device. Tested with SeaBIOS and memtest86+ master on Thinkpad X220. Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01payload/tianocore: Fix patch to preserve coreboot tableMatt DeVillier
Part of the original patch, commit 85a90e1, reverted edk2 commit: 1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED] which had the unintended effect of causing memory above 2GiB from being unavailable (marked reserved) when booting without a connected display (aka headles mode). This commit strips the patch to only the component needed to fix reading of the coreboot table low memory pointer. TEST: boot 4GB google/panther without connected display, verify memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m' Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-01payloads/tianocore: Add a patch to use the proper BytesPerscanlineArthur Heymans
This fixes tianocore garbled framebuffer when 'x_resolution * bits_per_pixel / 8' is not equal to 'bytes_per_line'. This patch was also send to the edk2-devel mailing list: https://lists.01.org/pipermail/edk2-devel/2018-January/020436.html Tested on Thinkpad X220 with libgfxinit on 1366x768 display. Change-Id: Ib9eaf692f86d416cd4ec3cc73a8b0aa0a28a38dd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-01-26libpayload: allow x86 devices to provide non-tsc implementationAaron Durbin
Make is so that a different timer source can be provided instead of TSC on x86 platforms. BUG=b:72378235,b:72170796 Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24payloads/nvramcui/payload.sh: Fix shellcheck warningsMartin Roth
In payloads/nvramcui/payload.sh line 5: DIR=`dirname $0` ^-- SC2006: Use $(..) instead of deprecated `..` ^-- SC2086: Double quote to prevent globbing and word \ splitting. In payloads/nvramcui/payload.sh line 6: lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1 ^-- SC2086: Double quote to prevent globbing and word \ splitting. ^-- SC2086: Double quote to prevent \ globbing and word splitting. ^-- SC2069: The order of \ of the 2>&1 and the \ redirect matters. The \ 2>&1 has to be last. Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23payloads/depthcharge: Update stable version upstream masterMartin Roth
Updating from commit id f3bb31fee: 2017-09-08 (vboot: Support EC early firmware selection) to commit 61cfcc3b: 2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2) This brings in 57 new commits. Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-22payload/Kconfig: Use LZMA by defaultArthur Heymans
With the tianocore payload on a Thinkpad X200 the filesize increased by approximately 50% and the time to fetch and decompress the payload increased by approximately %300 , so something is definitely wrong with it and it shouldn't be used as the default compression method. Change-Id: I9661c82750104d737596e7b3a8974324765938a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-15payloads: add support lz4 compressionAntonello Dettori
Add the option to use the lz4 compression method to compress payloads. Also sets LZ4 as the default compression method. Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-20payloads/SeaBIOS: Add different MMIO uart configurationsPhilipp Deppenwiese
The MMIO address can change for different platforms like Apollolake. Change-Id: I6ec72d3a14f00212323a04e20d5a477dbc26b770 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07libpayload: Add pci_free_dev() and some boilerplateNico Huber
Add just enough code and boilerplate to keep it compatible with future libflashrom. Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07payloads/external/Makefile: Add missing dependencyNico Huber
The depthcharge .config only exists after depthcharge was built. Other possible `PAYLOAD_CONFIG` files most probably miss a rule, too. Change-Id: I8e6f79bb2bd07cbef1317f2623bbef9ca0e74880 Signed-off-by: Nico Huber <nico.huber@secunet.com> Tested-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22137 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07libpayload: Add SKU ID coreboot table supportJulius Werner
This patch adds support to read the SKU ID entry from the coreboot table that was recently added in coreboot. Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22743 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07libpayload: Minor board ID / RAM code cleanupsJulius Werner
This patch mirrors recent cleanups in coreboot regarding the strapping ID entries in the coreboot table. Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-30payloads/external: Use stable version of GRUB2 by defaultJonathan Neuschäfer
Using the stable version by default is consistent with payloads/external/SeaBIOS. Change-Id: I444ba2daaf5ecc5edde907a7842013f88e1c4c9b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30payloads/external: Add a stable version of GRUB2Jonathan Neuschäfer
This should make reproducible builds of coreboot with GRUB2 easier. Change-Id: If855042945ab34f34c554e7490c811ec7b256980 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-28payloads/seabios: Update stable from 1.10.3 to 1.11.0Martin Kepplinger
SeaBIOS 1.11.0 was released on November 10th, 2017. Changes include * Initial support for NVME drives * Support for vga emulation over a serial port in SeaBIOS (sercon) * Support for serial debugging using MMIO based serial ports * Support for scsi devices with multiple LUNs * Support for boot-to-boot persistent coreboot cbmem logs * Improved coreboot vga (cbvga) mode setting compatibility * Several bug fixes and code cleanups See also https://www.seabios.org/Releases#SeaBIOS_1.11.0 and for all details on the changes, use git log --oneline rel-1.10.3..rel-1.11.0 in the SeaBIOS repository. Change-Id: Ie46a526593177c5241fbd979c7fa1934478f7382 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/22429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-08payloads/seabios: Update stable from 1.10.2 to 1.10.3Martin Kepplinger
SeaBIOS 1.10.3 was tagged on October 12th, 2017 with the following changes. ``` $ git log --oneline rel-1.10.2..rel-1.10.3 b7661dd tcgbios: Fix use of unitialized variable 6055583 boot: Increase description size in boot menu 3551613 resume: Don't attempt to use generic reboot mechanisms on QEMU ``` Change-Id: I3a9ebf10a55118fc35aed688ea7ec794333c8227 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/22358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-06endian: Fix bebitenc() to actually encode big-endianJulius Werner
bebitenc() just runs a downward loop over the same body as lebitenc(). That doesn't give you a byte-swapped result, it gives you the same final value, just starting from the other side to fill it in. (Also, it confused i++ and i--, so it really gives you a compiler error.) The correct code needs to have the array index inverted relative to the bit shift index to produce a big endian result. Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-29LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33Ronald G. Minnich
When building the Go version of cbmem I found that LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP. I am guessing that this tag was little used. In any event, move it forward to 0x33. Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/22218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-16payloads/external: Clone GRUB2 over HTTPSJonathan Neuschäfer
Since the git:// protocol is unencrypted and unauthenticated, there's a security risk associated with using it: A man-in-the-middle attacker could replace e.g. the master branch with malicious code. Mitigate this risk somewhat by cloning GRUB2 via HTTPS. Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-13Update vboot submodule to upstream masterDaisuke Nojiri
Updating from commit id 3f3a496a 2017-09-01 09:20:19 (image_signing: Fix loem.ini pattern for unibuilds) to commit id 753e34e9 2017-08-31 10:12:40 (futility: Make rwsig sign command produce EC_RW image) This brings in 5 new commits. This also updates Depthcharge stable commit ID. Updating from a843f262 2016-08-16 08:41:04 (kahlee: select emmc boot first if available) to commit id f3bb31fe 2017-08-15 17:15:33 (vboot: Support EC early firmware selection) This brings in 14 new commits. Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11payloads/coreinfo: Free buffer before returningMartin Roth
Fixes coverity issue 1373370 - Resource leak Change-Id: I71e0d3ae7f9152e1f89f8b3206526f0d344e0351 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-06tint: Use the current time as random seedNicola Corna
Previously the random seed was fixed, which led to the same sequence of blocks for each run. Now that libpayload has time(), no change is needed in the function rand_init() of tint. Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-02libpayload/storage: Add Sunrise Point AHCI PCI idNico Huber
Change-Id: I9645d76d05014722e4ae0c398d82f7f8e34d6f1c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-23Update depthcharge stable to upstream masterMartin Roth
Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017: (ps8751: enable software sync.) to commit id a843f262 - Wed Aug 16 23:37:52 2017: (kahlee: select emmc boot first if available) This brings in 20 new commits. This matches with the updated vboot submodule. Change-Id: If030bc3e75dd470838590540880213bd841154b8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-21libpayload: add time()Nicola Corna
Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-20payloads/external/GRUB2: Only rebuild on config changesNico Huber
Change-Id: I376eea9a3e02b03010fc5c5a05199ea7b2813220 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-18payload/tianocore: Add patch to preserve coreboot tableArthur Heymans
Credit for this patch goes to 'ReddestDream'. The patch is pulled from https://github.com/MattDevo/edk2 TESTED on thinkpad X200. Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-15payloads/Makefile.inc: Add GRUB2 to list of payloadsNico Huber
Change-Id: Iea4a609631ac2007b7b1845ff540abc912004be0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-15payloads/external/GRUB2: Sanitize MakefileNico Huber
We were explicitly passing CC and TARGET_CC to configure but overwrote that decision later by passing CC (with the value of TARGET_CC) directly to a recursive make call. The latter overwrite was introduced because `unexport` alone doesn't work on variables that were specified on a make command line (they are added to MAKEOVERRIDES and passed to further re- cursive make calls). Instead of unexporting random variables, unexport those that were actu- ally passed from payloads/external/Makefile.inc and clear MAKEOVERRIDES. Do not pass OBJDUMP as that is nowhere to be found in the GRUB sources. And, last but not least, add --disable-werror because building GRUB is very susceptible to changes in the flex version. Change-Id: Iaff2c72e89a5a540fe365eacb84811d5cff9d4d4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-14libpayload: add *SECS_PER_SEC macros to stddef.hCaveh Jalali
this adds convenience definitions for MSECS_PER_SEC, USECS_PER_MSEC, and USECS_PER_SEC along the lines of the time units in coreboot's <timer.h>. Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/20882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-11payloads/external/tianocore: Add and apply patches for tianocoreEvelyn Huang
Create a directory patches, and add necessary patches to be applied to upstream tianocore. Patches include: -Patch for no PCI address enumeration -Patches to enable keyboard input -Patch to disable serial to speed up boot process. Patches pulled from https://github.com/MattDevo/edk2. Additionally, modify tianocore Makefile to apply patches during build. Change-Id: I4eaa602418995a68753b1ed13af8c6374eaa312f Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-11copy & update test routines from what-jenkins-doesMartin Roth
Currently the only testing we had was 'what-jenkins-does' and 'make lint'. While the lint testing is suitable for developers, the 'what-jenkins-does' target really isn't, as it was designed specifically for testing on jenkins. This adds the infrastructure for basic tests that are more suitable for the developer. Extended tests and improvements will follow. Add the coreboot-builds directories to .gitignore. TODO: - Save/restore .config - Update test-abuild to use existing COREBOOT_BUILD_DIR variable Change-Id: I19e1256d79531112ff84e47a307f55791533806f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@google.com>
2017-08-10libpayload/libpci: Add a constant for PCI class memory otherNico Huber
Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10payloads/external/tianocore: build UEFI payloadMartin Roth
Update the existing tianocore payload (which didn't do any more than adding an elf payload with a specific name) to fetch and build the UEFI corebootPayloadPackage, using the coreboot toolchain for compilation. Only checkout the commit when changing commit IDs or if version is master, instead of every time it builds. Currently working if patches are merged into the upstream edk2 repository (to be included in a follow-on patch). Change-Id: I0bf4cedec2d6821ae2a04184ebb5cf88979ccee3 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Evelyn Huang <evhuang@google.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-10libpayload: Use a static copy of `font_glyph_filled()`Paul Menzel
libpayload needs a static copy of the out of line function `font_glyph_filled()` in every TU that needs it. So make it static inline. This fixes a build error by gcc (Debian 7.1.0-12) 7.1.0 from Debian Sid/unstable. This happens with any libpayload based payload like coreinfo, nvramcui or tint. ``` […] LPCC build/coreinfo.elf (LINK) /src/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(corebootfb.libc.o): In function `corebootfb_putchar': /src/coreboot/payloads/libpayload/drivers/video/corebootfb.c:173: undefined reference to `font_glyph_filled' […] ``` Change-Id: I931f0f17b33abafdc49aa755a0dad65e28820750 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/20897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-08add __must_check to */compiler.hCaveh Jalali
the __must_check function attribute is pretty much straight from the linux kernel - used to encourage callers to consume function return values. Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/20881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03libpayload: video: Add support for font scaling with a factorPaul Kocialkowski
This introduces support for font scaling with a factor provided via Kconfig. In practice, the font itself is not scaled at any point in memory and only the logic to determine whether a pixel should be filled or not is changed. Thus, it should not significantly impact either the access time or memory use. Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/20709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-03libpayload: video: Introduce helpers for font accessPaul Kocialkowski
This introduces helpers for accessing the included font, instead of using hardcoded values provided by the font's header itself. It will allow painlessly adding support for font scaling in a subsequent change. It should not introduce any functionality change. Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/20708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-28libpayload: Double HEAP_SIZE in default configRicardo Ribalda Delgado
Bettong board with the standard configuration is not capable of running nvramui with the default size. malloc error happens on PDC_makelines(). Resulting in: Booting from CBFS... Run img/nvramcui Calling addr 0x00100000 initscr(): Unable to create stdscr. exited with status 1 Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/20681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-27libpayload/storage: Replace 1s AHCI reset delay with a timeoutNico Huber
AHCI spec explicitly states that we may poll. TEST=Ran FILO on kontron/bsl6 and observed that the controller always becomes ready during the first delay. Change-Id: If34694abff14d719d10d89bc6771dbfa12065071 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-27libpayload/storage: Enable bus mastering for AHCINico Huber
This is (thankfully) not done by coreboot any more for recent chipsets. Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-26libpayload: Clean up unaligned memset() supportNico Huber
Use a `for` instead of a `while` loop and use meaningful identifiers. Also, don't use more than one variable for one and the same purpose, don't use more (non-const) variables than necessary, don't alter more than one variable per statement, don't compare pointers of different types and don't do pointer arithmetic on `void *`. This was meant as a fix up to a regression but that has already been fixed. Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-26payloads/depthcharge: Fix clean targetNico Huber
This line has a weird history. It got a `|| exit 0` removed lately which obviously was there to fix the presence of the superfluous `test` at the beginning. Now, remove the `test` too to make the clean target always succeed again ;) Change-Id: I9e069cf5d9ac8416cf350161439aa60798ef7b6b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-23depthcharge: Update buildMartin Roth
- Add prompt so the defconfig can be selected for the build. - Remove target rename code from makefile. The old versions don't build with the latest vboot, so this isn't useful anymore. - Change $(info ...) to an echo. info prints immediately when evaluated, which made it print when it shouldn't have, on make clean for example. - Split up single line shell scripts into multiple lines - Change checkout target to only update the commit id when actually changing versions instead of on every build. Change-Id: I46fc2822cf93c821b402e8961ceecedc088f486c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-23depthcharge: Update stable commit idMartin Roth
Update from commit eb583fa8 - Wed Mar 29, 2017 (rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz) to commit 5a086f5c - Tue Jul 11, 2017 (ps8751: enable software sync) This brings the stable version of depthcharge forward by 74 commits. Change-Id: I3a3719fa3a91824042d452de7774be85b884d96d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-20libpayload: Fix unaligned buffer logic in default_memsetMarshall Dawson
Fix an issue when setting an unaligned buffer where n is less than the difference of the rounded up pointer and the pointer. This was identified where n=1 was passed. n was decremented once, as expected, then decremented again after the while() evaluated to false. This resulted in a new n of 4GB. Change-Id: I862671bbe7efa8d370d0148e22ea55407e260053 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13libpayload: Support unaligned pointer for memcpy, memmove and memcmpJeremy Compostella
The memcpy(), memmove() and memcmp() functions use word by word operations regardless of the pointer alignment. Depending on the platform, this could lead to a crash. This patch makes the memcpy(), memmove() or memcmp() operate byte per byte if they are supplied with unaligned pointers. Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/20535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-12libpayload: Support unaligned pointers for memsetJeremy Compostella
The optimization of the memset() function introduced by commit dbadb1dd634c8c9419215ade0666a7fb69a4447b (libpayload: Reorder default memcpy, speed up memset and memcmp) is provoking an issue on x86 platform when compiling without the CONFIG_GPL option. GCC is making use of the movdqa instruction to copy words. This instruction can raise a "General Protection Fault Exception" when it is called on a non-aligned address argument. Change-Id: I73382a76a4399d8e78244867f2ebb1dca176a6bf Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/20524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-28libpayload: Add mouse cursor driverPatrick Rudolph
Add a driver to handle multiple low level mouse drivers and provide basic cursor acceleration support. Tested on Lenovo T500. Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28payloads: Add whitespace around '<<'Elyes HAOUAS
Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20396 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27libpayload/drivers/usb/ehci_private.h: Add brackets around macroElyes HAOUAS
Change-Id: Iee8dc03d5a4ca7537c7da4fed2c67b169c9e2422 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27libpayload/drivers/usb/xhci_private.h: Add parentheses around macroElyes HAOUAS
Change-Id: I0347594e9480dedc4845b6863733a67fc5e47e1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20371 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27coreinfo: Use regular `if` over `#if` for `IS_ENABLED`Nicola Corna
When using the regular `if` construct, the compiler will check the guarded code independently from the condition. Change-Id: I00c5c7ae3720f75aa9415edb94cd2ce76cee8aee Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27libpayload/drivers/usb/ohci_private.h: Add brackets around macroElyes HAOUAS
Change-Id: Id4892adba161cd08eecde71a011384b6c465b98f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27libpayload: corebootfb: Add null check for framebuffer addressDuncan Laurie
If the framebuffer address is zero the corebootfb_init() function should abort and not attempt to use it for video, otherwise it will likely hang. This was tested by booting on a board that does not have a display attached and includes the previous patch to zero the framebuffer structure in the coreboot tables. Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-26libpayload: Enable building libpayload with march=i586Lee Leahy
Add a Kconfig value to enable building libpayload with the 586 compiler. Update the cross compiler script to add the Kconfig value name that is used when libpayload builds. The Quark SOC does not support some of the instructions generated with the 686 compiler (e.g. CMOV). Success occurs when payloads/libpayload/build/config.h indicates that CONFIG_LP_USE_MARCH_586=1. TEST=Build and run on Galileo Gen2. Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26libpayload/configs: Add configuration for GalileoLee Leahy
Add the default configuration file for the Galileo board. The Quark SOC requires building libpayload with march=i586. TEST=Build and run on Galileo Gen2 Change-Id: Ifd4b533feacbab6f0d357e13d8cebb64bc1c18c6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07payloads/Kconfig: Add NO_DEFAULT_PAYLOADNico Huber
This symbol can be selected (e.g. in site-local/) to disable the user friendly but annoying default payload choice. Change-Id: I2f72d4efc0a428dce377c3d003b2c00a6c8d4c08 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19808 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-07payloads: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-07Use www.coreboot.org over coreboot.orgPaul Menzel
<https://coreboot.org> is redirected to <https://www.coreboot.org>. ``` $ curl -I https://coreboot.org HTTP/1.1 301 Moved Permanently Server: nginx/1.8.1 Date: Mon, 05 Jun 2017 10:41:33 GMT Content-Type: text/html Content-Length: 184 Connection: keep-alive Location: https://www.coreboot.org/ ``` So use the command below to use the final location to save a redirect. ``` $ git grep -l https://coreboot.org \ | xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g' ``` Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20035 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-06nvramcui: Use regular `if` over `#if` for `IS_ENABLED`Paul Menzel
When using the regular `if` construct, the compiler will check the guarded code independently from the condition. Change-Id: I988fa9379e8c748013a67ef29fa908b4d9a970ad Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for `HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model that with additional symbols. Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30arm64: Align cache maintenance code with libpayload and ARM32Julius Werner
coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-25detachables: Add invert parameterShelley Chen
Instead of storing inverted-colored bitmaps, invert drawing of text bitmap on the fly by adding an invert parameter down to libpayload. Merging pivot and invert fields into flags field. BUG=b:35585623 BRANCH=None TEST=Make sure compiles successfully CQ-DEPEND=CL:506453 Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-01cbgfx: Add portrait screen supportNickey Yang
cbgfx currently does not support portrait screen which height >width. so add it. Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19474 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-29libpayload/gdb: fix unused variable warningPatrick Georgi
input_underrun is defined but not used. A reasonably new compiler, enabled warnings and warnings-as-error make the build break for no good reason. Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/19482 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-04-20Turn CBMEM console into a ring buffer that can persist across rebootsJulius Werner
This patch allows the CBMEM console to persist across reboots, which should greatly help post factum debugging of issues involving multiple reboots. In order to prevent the console from filling up, it will instead operate as a ring buffer that continues to evict the oldest lines once full. (This means that if even a single boot doesn't fit into the buffer, we will now drop the oldest lines whereas previous code would've dropped the newest lines instead.) The console control structure is modified in a sorta backwards-compatible way, so that new readers can continue to work with old console buffers and vice versa. When an old reader reads a new buffer that has already once overflowed (i.e. is operating in true ring buffer mode) it will print lines out of order, but it will at least still print out the whole console content and not do any illegal memory accesses (assuming it correctly implemented cursor overflow as it was already possible before this patch). BUG=chromium:651966 TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco. Also confirmed correct behavior across suspend/resume for the latter. Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19libpayload/libc/console: Flush input driver buffer on initFurquan Shaikh
When console input driver registers itself, perform flush of input buffer to avoid interpreting any stale key presses before libpayload is run. keyboard.c: Remove the redundant buffer flush. 8250.c: Ensure that serial_hardware_is_present is set before call to add input driver. BUG=b:37273808 TEST=Verified that any key presses in serial console before payload is up do not have any effect after the payload starts running. Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-17libpayload: cbgfx: Show square images on portrait displaysJulius Werner
CBGFX currently doesn't support portrait screens at all. This will have to be fixed eventually but might take a bit of effort. As a first step to make devices with a portrait panel somewhat usable, this patch will just force a square canvas on these panels and keep the bottom part of the screen black. Also switch set_pixel to calculate framebuffer position via bytes_per_line instead of x_resolution. This is supposed to be the canonical way to do that and may differ in cases where the display controller requires a certain alignment from framebuffer lines. Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19279 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2017-04-17payloads/seabios: Update stable from 1.10.1 to 1.10.2Paul Menzel
SeaBIOS 1.10.2 was released on February 28th, 2017 [1][2] with the changes below. ``` $ git log --oneline rel-1.10.1..rel-1.10.2 5f4c7b1 QEMU fw_cfg: Write fw_cfg back on S3 resume c45ca70 QEMU fw_cfg: Add functions for accessing files by key 31b6229 QEMU fw_cfg: Add command to write back address of file aa7219d romfile-loader: Switch to using named structs 2a1d88c QEMU DMA: Add DMA write capability d2ac564 ps2port: Disable keyboard/mouse prior to resetting ps2 controller b0e3c67 vgasrc: Increase debug level ca3ab93 ahci: Set upper 32-bit registers to zero ``` This fixes the problem on a Lenovo X60, that the keyboard is not initialized by SeaBIOS when for example loaded from GRUB. [1] https://www.seabios.org/Releases#SeaBIOS_1.10.2 Change-Id: Idc078ffa896b2e105faabd2d8befeaf9a2a0b6ac Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/19290 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14payloads/external/depthcharge: Update stable commit idMartin Roth
Update from commit 124af94f - Fri Feb 26, 2016 (skylake boards: unconditionally re-enable 8254 PIT for legacy) To commit eb583fa8 - Wed Mar 29, 2017 (rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz) This brings the stable version of depthcharge forward by 325 commits. Change-Id: I31b3235df6d36409ff1b365e6adb6852281df097 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19220 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-14payloads/external/iPXE: Update stable versionMartin Roth
Update from commit 2afd66eb - Fri Jul 29, 2016 ([pixbuf] Enable PNG format by default) To commit fd6d1f46 - Fri Mar 31, 2017 ([thunderx] Use ThunderxConfigProtocol to obtain board configuration) This moves the stable iPXE commit forward 144 commits. Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19221 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-04-07libpayload: Add gru configPaul Kocialkowski
This adds a gru libpayload config, that should fit all gru-based devices such as kevin. As gru-based devices are CrOS devices, select the associated config to enable CrOS-specific features. Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/19137 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-19tint: Add USB supportNicola Corna
Enable the USB during the initialization of tint. Without it USB keyboards don't work, which makes this payload pointless on systems where a PS/2 keyboard port isn't available. Based on I98f0ccdb19d6b195572941cf87ce3221f57db7c5 (tint and nvramcui: enable USB, update tint to 0.04+nmu1 with changes) [1] [1] https://review.coreboot.org/17507/ Change-Id: Iaa8dfac0301ef19a2d76a0975d025b00e7f3807b Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18766 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-15libpayload: usbhub: Force enumeration of all connected ports on initJulius Werner
We have found a non-compliant USB hub (RealTek RTS 5413) that does not set a port's Connect Status Change bit on its USB 3.0 half if the port had already been connected while the hub was being reset. To work around this bug, this patch adds code to initially request the status of every port after a hub was enumerated, clear the Connect Status Change bit if set, and then enumerate the port iff it is currently connected, regardless of whether the change bit was set. A similar behavior can also be found in the Linux kernel. BRANCH=oak BUG=b:35929438 TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even if they had been plugged in since boot. Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18729 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-13nvramcui: Add USB supportNicola Corna
Enable the USB during the initialization of nvramcui. Without it the USB keyboards don't work, which makes this payload pointless on the systems where a PS/2 keyboard port isn't available. Based on https://review.coreboot.org/#/c/17507/ Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18765 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-08libpayload-x86: Enable SSE and FPU when presentPatrick Rudolph
Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-28payloads/seabios: Add support for Hudson UARTRicardo Ribalda Delgado
Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS supports memory mapped serial ports. This patch automatically configures SeaBIOS when the Hudson UART is enabled. Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/18025 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24payloads/external/GRUB2: Add "git revision" to the GRUB2 version menuDenis 'GNUtoo' Carikli
This change is based on the following commit: 3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/18352 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-23libpayload: Add oak configPaul Kocialkowski
This adds an oak libpayload config, that should fit all oak-based devices such as elm. Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/18447 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-17grub: Build module `boottime`Paul Menzel
Configure GRUB to build with boot time statistics. That allows users to add that module to GRUB by adding `boottime` to the list of extra modules. Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18367 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-02-17libpayload: multiboot - support meminfo flagMathias Krause
Some simple implementation of the MultiBoot protocol may not pass a memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO flag. Support those kind of boot loaders too, instead of falling back to the hard-coded values in lib_get_sysinfo(). Tested with a multiboot enhanced version of FILO. Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18350 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17libpayload: x86/head - implement argc/argv handlingMathias Krause
Implement the argc/argv passing as described in coreboot’s payload API: http://www.coreboot.org/Payload_API While at it, give the code some love by not needlessly trashing register values. Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-17libpayload: x86/exec - simplify and robustify the codeMathias Krause
Simplify the code by directly using the arguments on the stack as base pointer relative memory references, instead of loading them into intermediate registers first. Make it more robust by preserving all callee saved registers mandated by the C calling convention (and only those), namely EBP, EBX, ESI and EDI. Don't assume anything about the register state when the called function returns -- beside the segment registers and the stack pointer to be still the same as before the call. Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: https://review.coreboot.org/18335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)