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This patch adds support for the SuperSpeed half of USB 3.0 hubs, which
previously prevented SuperSpeed devices behind those hubs from working.
BRANCH=None
BUG=chrome-os-partner:39877
TEST=Played around with multiple hubs and devices on Oak and Falco, can
no longer find a combination that doesn't work.
Change-Id: I20815be95769e33d399b7ad91c3020687234e059
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e
Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284577
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com>
Reviewed-on: http://review.coreboot.org/10958
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We have been trying to avoid reassigning previously used USB addresses
to different devices since CL:197420, because some devices seem to take
issue with that. Unfortunately, that patch doesn't affect XHCI: those
controllers insist on chosing addresses on their own. The only way to
prevent them from reusing a previously assigned address is to not
disable that slot at all.
This patch implements address reuse avoidance on XHCI by not disabling
slots when a device is detatched (which may occur both on physical
detachment or if we simply couldn't find a driver for that device).
Instead, we just release as many resources as we can for detached
devices (by dropping all endpoint contexts) and defer the final cleanup
until the point where the controller actually runs out of resources (a
point that we probably don't often reach in most firmware scenarios).
BRANCH=none
BUG=chrome-os-partner:42181
TEST=Booted an Oak plugged into a Servo without having a driver for the
SMSC network chip, observed that it could still enumerate the next
device afterwards. Kept unplugging/replugging stuff until the cleanup
triggered and made sure the controller still worked after that. Also
played around a bit on a Falco without issues.
Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb
Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284175
Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10957
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With split transaction, dwc2 host controller can handle full- and
low-speed devices on hub in high-speed mode. This commit adds support
for split control and interrupt transfers
BUG=None
TEST=Connect usb keyboard through hub, usb keyboard can work
BRANCH=None
Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019
Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283282
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I8dfd8fbd452ce92fbca2cf095bc5e43e4a26969d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10920
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Write boot media information in sysinfo, if it exists. This allows picking the
right CBFS for further files in case there are several.
Change-Id: I75a8ee6b93f349b9f2fab1e82826aba675949c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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They will become more common soon, so better support them now.
Change-Id: I2b16e1bb7707fe8410365877524ff359aeefc161
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Well, this is just embarrassing...
BRANCH=None
BUG=None
TEST=None
Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d
Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284596
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10879
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Useful information, record it in the destination directory,
together with .config.
Change-Id: Icf3282f61f502b37f9f06d7d5a0a630f49c96ed2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10864
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Instead of having a second copy that already within 2-3 days
becamer quite outdated, use the same xcompile copy for coreboot
and libpayload, as we do with Kconfig already.
This requires a simple change to the top level xcompile to understand
both CONFIG_COMPILER_GCC and CONFIG_LP_COMPILER_GCC (only one of
them will occur at the same time)
libpayload's .xcompile target was moved later so that it can make use
of $(top)
Change-Id: I44001067f551cd0776dd303cbaeaa40eb3d5c1db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10863
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds support for the LZ4 decompression algorithm to
libpayload. It's what all the cool kids are using for decompression
these days and has many interesting advantages over LZMA (and everything
else I know of): blazing fast decompression (20(!) times faster than
LZMA, twice as fast as LZO on my Cortex-A72), no memory requirements on
decompression, and possibly in-place decompression support. It pays for
that with a lower compression ratio (about 50% larger compressed size
than LZMA, 10% larger than LZO for an ARM64 Linux kernel binary), but
the boot time math still works in its favor for our IO speeds.
This patch only adds the raw decompression functions for use by external
payloads, we can later try integrating them in CBFS. It copies the
decompression code itself unmodified from the upstream LZ4 library at
github.com/Cyan4973/lz4 which will hopefully make it easy to update. The
frame format parsing is reimplemented since the upstream version looks
unnecessarily complex and unreadable for our needs.
BRANCH=smaug
BUG=chrome-os-partner:32184
TEST=With other patches, booted ARM64 kernel that got compressed from
15M to 5.1M and decompresses in 44ms.
Change-Id: I65bdc4b2b19bd51c7b7e17a4e4b79da301a2a014
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8a1fc996d5b0234d07f567fa8163d0f802d5144
Original-Change-Id: I15c0620da05561ade2552b15ffdf6bb3afd7eb26
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282743
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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That way they don't need an initial 'make oldconfig' pass to
be useful again.
Change-Id: I3724fffab24b69478b8077f34e9d787555fd157b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10805
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Makefile already sets it to contain the architecture specific flags,
don't drop them, but add to that instead.
Change-Id: I147e6480ab2b3c1ee4f4ace511197b4ba94280b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10804
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This helps the build system find i386 and mips compilers.
Change-Id: I17d18019b556190f860d288e66f368f8d29ca24d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10803
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's unused. If we need something like that, .xcompile provides it,
and in a cross-platform and clang-aware way.
Change-Id: Ic1bdc2e3e252d612a5b99ad4e8caebc5158a485f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10802
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It needs to come after DOTCONFIG so that the compiler decision can
be made.
Change-Id: I5c6730ac58ab8731f07bb7c5161b2d0a59588e28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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clang is totally untested, but it mirrors coreboot now.
Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10800
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I97088df1550f580d4648c7cccbd81c696fcfe2dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10799
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To allow a payload to define its own libpayload_init_default_cbfs_media,
default implementation needs to be defined weakly.
BUG=none
BRANCH=tot
TEST=dumped a cbfs file from depthcharge cli on jerry
Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352
Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This will conflict with struct spi_flash defined in spi_flash.h
BUG=none
BRANCH=tot
TEST=built libpayload for veyron jerry
Change-Id: I7e1be28cf430021944fc96890082a0704d093e9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520
Original-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282588
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10782
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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IS_ENABLED is defined in kconfig.h, thus, should be included in
libpayload.h.
BUG=none
BRANCH=tot
TEST=built coreboot/libpayload for veyron_jerry
Change-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6
Original-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282587
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10781
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The LZMA functions are supposed to return the decompressed size, but
what they actually return is just an unaltered field from the LZMA
header that is *supposed* to contain the decompressed size. Apparently
some encoders just overshoot that for no good reason. This patch changes
the code such that the actual amount of decompressed bytes is returned.
BRANCH=smaug
BUG=None
TEST=Printed output bytes when decompressing kernels with LZMA in
depthcharge, noted that amounts now make sense.
Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263
Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282742
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10777
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.
BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None
Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This applys the same change made by
https://chromium-review.googlesource.com/261692
to libpayload.
BUG=none
BRANCH=tot
TEST=built for veyron_jerry, rush_ryu, samus
Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030
Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282541
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add force_shutdown() routine for dwc2 udc driver to support
disconnect and reconnect case when fastboot receiving data.
BUG=chrome-os-partner:41687
BRANCH=None
TEST=None
Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9
Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281130
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Copy from coreboot. at some point it probably should just reuse coreboot's
version.
Change-Id: Iee905a9060983ff85e2e70bde69a221c64a07cbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Always compile with -ffunction-sections and -fdata-sections
This does not hurt, and it allows the linker to produce much
smaller binaries in some circumstances.
Change-Id: Ibf9f24c210d6d2ed40451b4cf0d68ce88220bc5f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Without this, gdb_enter() is not defined.
Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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There is no measurable performance impact, but
this positively impacts the memory used by payloads.
Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10751
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ia451e8250307ad1944cb0429bdfee4bdf18c706b
Reviewed-on: http://review.coreboot.org/10712
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It's perfectly fine to have one single copy of kconfig in the tree.
Change-Id: Icfe32f0249dfc1c223009d6e7136462f8f8a7248
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This will make the code work with the different styles
of Kconfig (emit unset bools vs don't emit unset bools)
Roughly, the patch does this, and a little bit of fixing up:
perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]`
perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]`
Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10711
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The macros of VT100_CURSOR_ON and VT100_CURSOR_OFF are exchanged
Change-Id: Ifdae186ae0503a915d695a9e3fd24bdf65d8428a
Signed-off-by: House Chou <hoare.tw@gmail.com>
Reviewed-on: http://review.coreboot.org/10718
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Found in rockchips rk3288 as used in google/veyron.
BUG=None
TEST=None
BRANCH=None
Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1
Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272108
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:41687
BRANCH=None
TEST=Compiles successfully and fastboot devices reports correct serial
number even after re-connection.
Change-Id: I4741a5d6333523eb47c27b4a20c4ef3f1e853d76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6249b1e35391550d788f56a7b3e7a49ae19f0c93
Original-Change-Id: I1348c33f354d11e3c29ccd9da9948cfbeb60aa9e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281192
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10687
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Allow force shutdown operation of the connection in case where the
cable is disconnected and reconnected back.
BUG=chrome-os-partner:41687
BRANCH=None
TEST=Compiles successfully and fastboot works fine even with
reconnection of cable
Change-Id: I8eb1217b4a9ad6ce8a2a40db329eca1930eda089
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d7ab65c459caa4ec526b99a1aee1a31e9cb80da
Original-Change-Id: I354c44e0ed2211cb2c4c1ae653d201b7d15ea932
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281066
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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They're ASCII only, with only one language at a time,
but they should be good enough to report device names and
serial numbers.
BUG=none
BRANCH=none
TEST=with depthcharge CL, check dmesg on the host device
Change-Id: If888e05b2f372f7f0f43fadb108ca7ef4ed3b7c1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f0bc4242057d3edc4f4796ebeed2d98d89d60a1d
Original-Change-Id: Ibe42f1b49f412e5482cebb7ebe20f6034352fd12
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/278300
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10626
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Parse coreboot table and fill in mtc_start and mtc_size values in
sysinfo structure.
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: If210ea0a105f6879686e6e930cb29e66bc5e6cd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b70d0d35c85fa1a2317b0239276d5d9e7a550472
Original-Change-Id: I60b6f8ed4c704bd5ad6cce7fce2b9095babe181e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276778
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10563
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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Add macro to calculate size of a structure member
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully
Change-Id: I71bcefe1c3b32ad559d7764e77369c67d09422a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b425a310c14eabad79caf97649db6469380bd602
Original-Change-Id: I377fff062729aa664f7db469b86764b0ad941c38
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276809
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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libpayload is the only Kconfig based project under
the coreboot umbrella that is using Config.in as its
name for Kconfig config files. Rename that to Kconfig
as on the other projects for consistency.
Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
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Who knows it still?
Change-Id: If6e36569cd9a1ba3da8b3fe84264cd2a6dfd634b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10443
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
|
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Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds a few bit counting functions that are commonly needed
for certain register calculations. We previously had a log2()
implementation already, but it was awkwardly split between some C code
that's only available in ramstage and an optimized x86-specific
implementation in pre-RAM that prevented other archs from pulling it
into earlier stages.
Using __builtin_clz() as the baseline allows GCC to inline optimized
assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and
to perform constant-folding if possible. What was previously named log2f
on pre-RAM x86 is now ffs, since that's the standard name for that
operation and I honestly don't have the slightest idea how it could've
ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm
with Float result, whereas the Find First Set operation has no direct
correlation to logarithms that I know of). Make ffs result 0-based
instead of the POSIX standard's 1-based since that is consistent with
clz, log2 and the former log2f, and generally closer to what you want
for most applications (a value that can directly be used as a shift to
reach the found bit). Call it __ffs() instead of ffs() to avoid problems
when importing code, since that's what Linux uses for the 0-based
operation.
CQ-DEPEND=CL:273023
BRANCH=None
BUG=None
TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new
log2() and __ffs() results on Falco for a bunch of test values.
Change-Id: I599209b342059e17b3130621edb6b6bbeae26876
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f
Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/273008
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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1. There is a mis-understanding to calculate the value of TD Size
in Normal TRB. For MTK's xHCI controller it defines a number of
packets that remain to be transferred for a TD after processing
all Max packets in all previous TRBs, that means don't include the
current TRB's.
2. To minimize the scheduling effort for synchronous endpoints in xHC,
the MTK architecture defines some extra SW scheduling parameters for
HW. According to these parameters provided by SW, the xHC can easily
decide whether a synchronous endpoint should be scheduled in a specific
uFrame. The extra SW scheduling parameters are put into reserved DWs
in Slot and Endpoint Context. But in coreboot synchronous transfer can
be ignored, so only two fields are set to a default value 1 to support
bulk and interrupt transfers, and others are set to zero.
3. For control transfer, it is better to read back doorbell register or add
a memory barrier after ringing the doorbell to flush posted write.
Otherwise the first command will be aborted on MTK's xHCI controller.
4. Before send commands to a port, the Port Power in PORTSC register should
be set to 1 on MTK's xHCI so a hook function of enable_port in
generic_hub_ops_t struct is provided.
Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41
Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265362
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10389
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
|
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BRANCH=none
BUG=none
TEST=none
Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409
Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/269863
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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|
The lack of a div_round_up() function in libpayload keeps being a
problem for payloads and has already caused us to sprinkle numerous
less-readable ALIGN_UP(n, d) / d throughout depthcharge. Let's add this
so we can avoid adding any more and then maybe cocchinelle them all over
later.
BRANCH=None
BUG=None
TEST=None
Change-Id: I241a52770a0edcf7003b48a81875b3fa0cb7ed53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3f9514f9cfd325cc3c4b542020574b605fac935
Original-Change-Id: Ia55bd4bc52ab8a249b4854e40727cf6917af7b30
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/273050
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10392
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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|
The current arm64 MMU interface is difficult to use in pre-RAM
environments. It is based on the memranges API which makes use of
malloc(), and early stages usually don't have a heap. It is also built
as a one-shot interface that requires all memory ranges to be laid out
beforehand, which is a problem when existing areas need to change (e.g.
after initializing DRAM).
The long-term goal of this patch is to completely switch to a
configure-as-you-go interface based on the mmu_config_range() function,
similar to what ARM32 does. As a first step this feature is added
side-by-side to the existing interface so that existing SoC
implementations continue to work and can be slowly ported over one by
one. Like the ARM32 version it does not garbage collect page tables that
become unused, so repeated mapping at different granularities will
exhaust the available table space (this is presumed to be a reasonable
limitation for a firmware environment and keeps the code much simpler).
Also do some cleanup, align comments between coreboot and libpayload for
easier diffing, and change all error cases to assert()s. Right now the
code just propagates error codes up the stack until it eventually
reaches a function that doesn't check them anymore. MMU configuration
errors (essentially just misaligned requests and running out of table
space) should always be compile-time programming errors, so failing hard
and fast seems like the best way to deal with them.
BRANCH=None
BUG=None
TEST=Compile-tested rush_ryu. Booted on Oak and hacked MMU init to use
mmu_config_range() insted of memranges. Confirmed that CRCs over all page
tables before and after the change are equal.
Change-Id: I93585b44a277c1d96d31ee9c3dd2522b5e10085b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f10fcba107aba1f3ea239471cb5a4f9239809539
Original-Change-Id: I6a2a11e3b94e6ae9e1553871f0cccd3b556b3e65
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271991
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
|
|
Change-Id: Ifb19cf97d4db6c7394521e549968a0cfb6ed1c75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0137652ca07e290bb3cb1cc82a00b44ac7bcc7bf
Original-Change-Id: Ica649927d3533c847b24e520e8fe73d75fb9e786
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/257375
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
libpayload on x86 defines u32 and uint32_t as typedefs of
unsigned int. However, the readl/writel routines use long.
With alias checking this throws type punning errors. Align
the readl/writel/inl/outl types with the 32-bit fixed width
ones that are exposed.
Change-Id: Ie51cff8af4596948f6132e3cb743f1bc4ea8f204
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10186
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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The EHCI driver never looked for the base address handed to
it but instead used an uninitialized field for that information.
Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Make the XHCI driver compile on ARM again. The Panther Point
specific shutdown handler is certainly _not_ necessary there.
Change-Id: I470afd4d82d101902b119b3ead4381e2b36a94b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10091
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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1. change mmu granule size from 64KB to 4KB
2. correct level 1 translation table creation logic
3. automatically calculate granule size related macros
BRANCH=none
BUG=none
TEST=boot to kernel on oak board
Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38
Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/266010
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: http://review.coreboot.org/10010
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
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arch_program_segment_loaded ensures that the program segment loaded is
synced back from the cache to PoC. dcache_flush_all on arm64 does not
guarantee PoC in case of MP systems. Thus, it is important to track
and sync back all the required segments using
arch_program_segment_loaded.
BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on smaug
Change-Id: Ic6fcc7e5e0cccbab317950f8abab0c494041d19a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 284e3784854f764159b64286cea366c66b6bce2c
Original-Change-Id: I5c35b9aa2ae9b5c1f2fcdef40ffb1cde7f49cc1a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263327
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.
BUG=chrome-os-partner:38231
BRANCH=None
TEST=Compiles successfully for smaug and boots kernel
Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529
Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9903
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:38222
BRANCH=None
TEST=Compiles successfully and boots kernel
Change-Id: I6e1e841d84d1a73e5c726143aeba76af933e81a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59861a2700407b9e6a6209fbc45543c127b50b4b
Original-Change-Id: I256d07a41bec83037f2b61a9350f903119d8c101
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/263325
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9902
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
size_t is an unsigned type and as such is a bad choice for a counting
down loop counter.
BRANCH=all
BUG=none
TEST=editing cli command line does not cause hangs any more
Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b
Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262714
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Add serial number to lib_sysinfo from coreboot table.
BRANCH=none
BUG=chrome-os-partner:37813
TEST=ryu boots and /proc/device-tree/firmware/android is populated
with "compatible", "hardware", and "serialno" properties
Change-Id: I565b332a16b177c51907ffab7976ebd7a665aaaf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5535119f5d499b04bdc178c3040241d2872c4e13
Original-Change-Id: Ie2e222780d1577689a1cbf76ae8514c74fc469f4
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/259140
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Since CL:170664, all SC_SPEED_XXX renamed to SC_SPEED1_XXX.
There is one missing in xhci_dump_slotctx() function which makes
compilation error.
BUG=none
TEST=enable USB_DEBUG and XHCI_DUMPS macros in xhci_private.h;
then emerge-auron libpayload
Change-Id: Ib96805cb7fc1cad17b205277539fb2120632f6f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ca0174e93ad131309ad07187c95c1e84c7d4fc5
Original-Change-Id: Id056b4684831a5717e87969e95ab17f11db29696
Original-Reviewed-on: https://chromium-review.googlesource.com/261414
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Harry Pan <harry.pan@intel.com>
Original-Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: http://review.coreboot.org/9877
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:36011
BRANCH=broadcom-firmware
TEST=measured 10 seconds in depthcharge:
Starting depthcharge on purin...
dpch: time 10
9 8 7 6 5 4 3 2 1 0
Change-Id: I0bcb01c255b19518bb8440111ac81f056c07ed69
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f5993bd400dd5d38e62d07bc8ce3513175e0d518
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200569
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Change-Id: Id83aae29cec6320d897e0b231d023a9ee885903e
Original-Reviewed-on: https://chromium-review.googlesource.com/256415
Reviewed-on: http://review.coreboot.org/9850
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:35807
BRANCH=broadcom-firmware
TEST=tested input and output by the cli in depthcharge
Change-Id: Icd517a366a3fe5bdcf9e9aeb4284d7e4378ee3f2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 02c3b6c82d9d71beb19a0879591c754fa7685362
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200568
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Change-Id: I97144fc6f19969b8cf3872939c9c74efaef3604b
Original-Reviewed-on: https://chromium-review.googlesource.com/256413
Reviewed-on: http://review.coreboot.org/9844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The WG (write gate) bit in C0_EBase allows the upper two bits of
the exception base address to be set to something other than 2'b10,
thus allowing it to be relocated out of the traditional KSEG{0,1}
range. Since we're not using the segmentation features introduced
by EVA to relocate the unmapped segments, the exception vectors
should remain in KSEG0. Don't set the WG bit so that the upper
two bits of the exception base (2'b00, because of the identity
mapping) are ignored and we execute the exception vectors out of
KSEG0.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea
Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246697
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9822
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Add helper macros to convert between physical addresses and KSEG{0,1}
addresses. Also get rid of the virt_to_{bus,phys}_offset variables
as these are fixed values.
As nobody seems to be using getpagesize() on MIPS, no need to keep
virtual.c.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: Ia26c8eae53eb8f860747a6b321363776841d1a94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c422b02e9a2a20d130913b1cfb835ad74c39ddca
Original-Change-Id: I9476cd225a08534830c700cba7bf9d3ef871757e
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247190
Reviewed-on: http://review.coreboot.org/9821
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use bus_to_virt() to convert the physical address of the DMA
coherent region to an address in KSEG1 which is suitable for
device memory accesses.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: If382feda66f6d829f8b3548ab263cf603cab2e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a88a175f6d6db81d3154fb5dd31a44363ab94653
Original-Change-Id: I9ad6435495df2c71d8f81a782f1c3dfcfd4aeb28
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246696
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9818
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Now that coreboot has identity-mapped DRAM, use base address 0 (KUSEG)
instead of 0x80000000 (KSEG0).
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: I39845250a1b8cea6e5360efce16770751ffce13d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c1cbc1d7f6873c0be30d4206a2030f3b468acf24
Original-Change-Id: I76d98664f1bca73ae8acc9f545e68de9173c3cab
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246695
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9817
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
I doubt anybody will ask for the configuration and request that
0 bytes be returned, but AFAICS that's legal, so let's support it.
Should have no effect on ChipIdea since it knows not to send more
data than requested by the host.
BRANCH=none
BUG=none
TEST=none
Change-Id: Ibfe57b593015fa5e0381c45ff9e39c3f912b4d4d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45555e929d9d07dbb58ecfd18333f26375a0e3d7
Original-Change-Id: I7432772a1812c6f52c2b1688ee4c6f67d02ccf28
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258064
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9790
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Only set internal variables when there's no risk of breaking things.
BRANCH=none
BUG=none
TEST=none
Change-Id: I8a8b63f60bdb70fad38130ce38eef81fe3725aa2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7119829096b444b790937b116fb782bcb5da70cd
Original-Change-Id: If698b11a7ff7688def310d8574fcfa7a40f703c1
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258063
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9789
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
First handle IN packets, then OUT packets and finally SETUP packets.
This makes OS X happy. It isn't implemented as the data sheet recommends
but it avoids implementing a state machine and should always produce
observable effects identical to that of the stateful solution.
BRANCH=none
BUG=none
TEST=`fastboot getvar version` on OSX works
Change-Id: Ic7b27387771d6a7794fba12fc822fccc48770ea8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f0e59547519d50b1d34f6abdc6132330125f94f3
Original-Change-Id: Iada1cff011f11e7d5cb1a1b34896ab590f488ec7
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258062
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9788
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Mark EP0 non-stall explicitly. Shouldn't be necessary, but
won't hurt either.
BRANCH=none
BUG=none
TEST=none
Change-Id: I7ecd16a2affe064918d93436aedfa07bd9a1cf56
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a0fc237b33444fc30dc5b62e4f1afc3188f2cf43
Original-Change-Id: I1aa8742eebc4de733317600e35627631ebaf4724
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258061
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9787
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Trivial copy & paste error, likely with no visible effect so far.
BRANCH=none
BUG=none
TEST=none
Change-Id: Ieaf5e770ab7a8474e407012d2c11a15c46ab357d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 90f8971500c95456ae70c6f4219b1ff9aff1c0b0
Original-Change-Id: I973573efd0effc9e0173d2b259ce577b6de38de4
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258060
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9786
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
SET_CONFIGURATION(0) stops operation and is moves the
device to addressed mode.
BRANCH=none
BUG=none
TEST=USB device mode still works
Change-Id: I964d90ba8440b6f428896acc9fe63e1114390da6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 402bc907222d07765b3438967edf26cc1a79d775
Original-Change-Id: Iebad024e1ed2e344dba73b73a9b385a4ac4cb450
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/250791
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Some IN transfers must be terminated by an empty packet
because otherwise the host wouldn't know.
The zlp() function determines this requirement in
accordance to USB rules: If the transfer's size is aligned
to the maximum packet size, and the host expects a larger
transfer, add the empty packet as a hint.
BRANCH=none
BUG=none
TEST=USB device mode still works
Change-Id: Ia69f3d017f72a3a0e0b21bac72fe97be184c7daa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd0e946e4948a74a9ed15a5eed6ce827b7672a56
Original-Change-Id: I8153cc5bd2ff1c88e383c1dbcddaf1bf72f9194c
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/250790
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Add a framework for USB device mode controllers
and a driver for the ChipIdea controller which
is part of the tegra platform.
TODO:
- fix USB detach/attach
- implement zero length packet handling properly
BUG=chrome-os-partner:35861
TEST=none
BRANCH=none
Change-Id: I8defeea78b5a3bdbf9c1b1222c2702eaf3256b81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 542332291880c4026a05a960ceb91d37891ee018
Original-Change-Id: Ib4068d201dd63ebeda80157bd3130f3059919cdd
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/243272
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=none
BRANCH=tot
TEST=emerge-purin libpayload depthcharge coreboot chromeos-bootimage
Change-Id: I6a46067a288ecea352a2724c62c62066e3f4a383
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 355371317dde0546fbab2cd109bc17463f77c4fd
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I8c43acc4d270c3b2d7c18af07c077a553e3c6f6f
Original-Reviewed-on: https://chromium-review.googlesource.com/245492
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9753
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.
Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
There was a recent patch by Deepa Dinamani applied to coreboot's
cache.c which fixed a bug that occurred when icache is on but dcache
is off ("arch: armv7: Fix cache sync instructions."). Although this
bug is not likely to be encountered by the time libpayload is run,
it's worth applying it to keep things in sync.
BUG=none
BRANCH=none
TEST=n/a since we have icache and dcache enabled on all ARM platforms
when libpayload is run.
Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40
Original-Reviewed-on: https://chromium-review.googlesource.com/243276
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
A payload may want to run erase operations on SPI NOR flash without
re-probing the device to get its properties. This patch passes up
three properties of flash to achieve that:
- The size of the flash device
- The sector size, i.e., the granularity of erase
- The command used for erase
The patch sends the parameters through coreboot and then libpayload.
The patch also includes a minor refactoring of the flash erase code.
Parameters are sent up for just one flash device. If multiple SPI
flash devices are probed, the second one will "win" and its
parameters will be sent up to the payload.
TEST=Observed parameters to be passed up to depthcharge through
libpayload and be used to correctly initialize flash and do an erase.
TEST=Winbond and Gigadevices spi flash drivers compile with the changes;
others don't, for seemingly unrelated reasons.
BRANCH=none
BUG=chromium:446377
Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126
Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239570
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This adds a directory with files copied over from Brain along with
build-related changes so that emerge-veyron_danger works. The next
patch will account for other differences.
BUG=none
BRANCH=none
TEST=emerge-veyron_danger coreboot works
Change-Id: I7ebd431cd48e257dfa761d32013d0e251b4f155d
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a0f7d2f96540df6fdcd7a99d9e0fa02bbc6c1f73
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id265a7715f07a647a449f00097bf40f7c9b4c068
Original-Reviewed-on: https://chromium-review.googlesource.com/241711
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
This adds a directory with files copied over from Jerry, in addition to
build system related changes (configs/* and Kconfig stuff) necessary
to emerge-veyron_brain coreboot.
The next patch will account for differences between Jerry and Brain.
BUG=none
BRANCH=none
TEST=emerge-veyron_brain coreboot works
Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36
Original-Reviewed-on: https://chromium-review.googlesource.com/236989
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9637
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
|
|
make oldconfig doesn't like 'y' as response to a choice item
such as the architecture list. An empty response, however, is
acceptable, so use that.
Change-Id: Ic3164dd3f40e4a7f5d91e3a7008893655cd69ac2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9676
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Extended the 32bit CPU counter to 64bit by adding a static
variable that takes into account CPU counter overflow.
The varibale is updated everythime the timer_raw_value
function is called so I assume that the function is called
often enought to not miss an overflow of the CPU counter.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; works as expected
BRANCH=none
Change-Id: I98bcc56e600dcff0c6da7c140dd34faec5e00885
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 972b105f950d800fa44f27bce090f6b89a5a84b9
Original-Change-Id: Id67b14e9d9c2354bc417b6587b615d466690c9b7
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/247642
Original-Reviewed-by: Daniel Ehrenberg <dehrenberg@chromium.org>
Reviewed-on: http://review.coreboot.org/9672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
BUG=None
BRANCH=None
TEST=Download and write to kernel partition successful on ryu
Change-Id: I9623a0a430e95633dabbb87537a5c70bc9619dde
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 3ba52d7c7baa42de3149cc604423a5825988401e
Original-Change-Id: Ia6ba5ad52596c32cc3ad42f98c7f4f8b3e13d6c5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242205
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9661
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The address of the output buffer sent to the device should be
the bus address and not the virtual address.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA and bring up board;
USB works properly after this change
BRANCH=none
Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438
Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245387
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9455
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Total FIFO length is split into 512 byte blocks.
Allocate these blocks to GRXFSIZ and GNPTXFSZ evenly.
This method avoids hardcoding and makes the FIFO size value
work for dwc2 controllers that have a different FIFO ram size.
BUG=chrome-os-partner:32634
BRANCH=None
TEST=Boot kernel from USB
Change-Id: I78ce0fa4c4600fb56c991874a93bdd6674e648c2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5645a25e95f84359cd10fc9fcf56e1f73fd6ce87
Original-Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233119
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9454
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
BUG=chrome-os-partner:29778
TEST=emerge-veyron libpayload
Change-Id: I33f312a939e600b8f4e50a092bb61c5d6bc6d741
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39ffe53336a2a3b2baa067cdd3dccca5ae93f68e
Original-Change-Id: Idad1ad165fd44df635a0cb13bfec6fada1378bc8
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211053
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Non-x86 boards currently need to hardcode the position of their CBFS
master header in a Kconfig. This is very brittle because it is usually
put in between the bootblock and the first CBFS entry, without any
checks to guarantee that it won't overlap either of those. It is not fun
to debug random failures that move and disappear with tiny alignment
changes because someone decided to write "ORBC1112" over some part of
your data section (in a way that is not visible in the symbolized .elf
binaries, only in the final image). This patch seeks to prevent those
issues and reduce the need for manual configuration by making the image
layout a completely automated part of cbfstool.
Since automated placement of the CBFS header means we can no longer
hardcode its position into coreboot, this patch takes the existing x86
solution of placing a pointer to the header at the very end of the
CBFS-managed section of the ROM and generalizes it to all architectures.
This is now even possible with the read-only/read-write split in
ChromeOS, since coreboot knows how large that section is from the
CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be
changed on systems that place other data next to coreboot/CBFS in ROM).
Also adds a feature to cbfstool that makes the -B (bootblock file name)
argument on image creation optional, since we have recently found valid
use cases for CBFS images that are not the first boot medium of the
device (instead opened by an earlier bootloader that can already
interpret CBFS) and therefore don't really need a bootblock.
BRANCH=None
BUG=None
TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco.
Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c
Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229975
Reviewed-on: http://review.coreboot.org/9620
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
We have two drivers for a 100%-identical peripheral right now, mostly
because we couldn't come up with a good common name for it back when we
checked it in. That seems like a pretty silly reason in the long run.
Both Tegra and Rockchip SoCs contain UARTs that use the common 8250
register interface (at least for the very basic byte-per-byte transmit
and receive parts we care about), memory-mapped with a 32-bit register
stride. This patch combines them to a single 8250_mmio32 driver (which
also fixes a problem when booting Rockchip without serial enabled, since
that driver forgot to check for serial initialization when registering
its console drivers). The register accesses are done using readl/writel
(as Rockchip did before), since the registers are documented as 32-bit
length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce
APB accesses to have the full word length. Also fixed checkpatch stuff.
A day may come when we can also merge this driver into the (completely
different, with more complicated features and #ifdefs) 8250 driver for
x86 (which has MMIO support for 8-bit register stride only), both here
and in coreboot. But it is not this day. This day I just want to get rid
of a 99% identical file without expending too much effort.
BUG=None
TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial
enabled, both worked fine (although Veyron has another kernel issue).
Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8
Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225102
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9387
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Don't attempt to scan the PCI bus if the bridge is disabled. When
the PCI bridge is not setup and enabled, it is possible for the
secondary bus register to contain the value zero (0). In this case
the usb_scan_pci_bus routine gets into an infinite recursive loop
which ends only when the heap or stack is exhausted. This patch
verifies that the PCI bridge is enabled by verifying that it is
enabled for either memory or I/O operations. When enabled, the
secondary bus is scanned.
BRANCH=none
BUG=None
TEST=Build and run on Samus
Change-Id: I6826dc1d73b7c24729de5ac7c4d3534922ca73c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 63d04b47934761351b54c847a2692bdef81ce54f
Original-Change-Id: I855240c52fa3eba841e6754816ebbcb824abc4cd
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/236382
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:32772
BRANCH=none
TEST=Built chromeos-bootimage
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1
Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7
Original-Reviewed-on: https://chromium-review.googlesource.com/222662
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9360
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Paging code is tricky and figuring out what is wrong with it can be a
pain. This patch tries to ease the burden by giving a little more
information for prefetch and data aborts, dumping the Instruction Fault
Address Register (IFAR), Instruction Fault Status Register (IFSR) and
Auxiliary Instruction Fault Status Register (AIFSR) or the respective
Data registers. These contain additional information about the cause of
the abort (internal/external, write or read, fault subtype, etc.) and
the faulting address.
BUG=None
TEST=I have read through enough imprecise asynchronous external abort
reports with this patch that I learned the bit pattern by heart.
Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c
Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223784
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
If a TD is comprised of one or more Normal TRBs and terminated with an
Event Data TRB, then the transition to the Idle state (and associated
Stream state save) could occur after all the data for the TD has been
moved (e.g. after Transfer Event TRBs have been executed), but before the
Event Data TRB is executed. Under these conditions, the execution of the
Event Data TRB is necessary to complete the TD, otherwise it does not
occur until the next time the Stream is scheduled. This could lead to the
lock up.
The Evaluate Next TRB(ENT) flag provides a means of forcing the execution
of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes
the xHC to evaluate the Even Data TRB.
BUG=chrome-os-partner:29375
TEST=Verified kernel boot-up on storm from previously failing USB stick.
USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB
Strontium Jet USB 3.0 Pen Drive 32 GB
Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8
Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220123
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
If EHCI controller has TT (Transaction Translator) support in
root-hub, then we need to keep control over this controller when
USB keyboard (low-speed device) is connected to root-hub port.
Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file
(e.g. payloads/libpayload/configs/config.nyan_big) to support this
feature.
BUG=chrome-os-partner:32355
TEST=Tested on nyan_big platform.
Press ESC+REFRESH+POWER keys on internal keyboard to power up.
Press Left Arrow or Right Arrow on USB keyboard to switch between
"English" and "Default Locale" in coreboot UI. Or unplug and plug
in device and try again.
Root hub <- low-speed USB keyboard
Root hub <- full-speed hub <- low-speed USB keyboard
Root hub <- high-speed hub <- low-speed USB keyboard
Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b
Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983
Original-Signed-off-by: Jim Lin <jilin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/220125
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Instead of forcing boards to have DMA region below 4GiB, provide
Kconfig option DMA_LIM_EXCL that a board can use to set the upper
limit in MiB units on the address range reserved by DMA. By default,
this value is 0x1000 i.e. 4GiB limit on the DMA upper address.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Default value is seen as 0x1000.
Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3
Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245250
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8800
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Align struct members with tabs.
Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The raw_write_sctlr_current() cannot be used in mmu_disable() because
it pushes some registers to cached stack, and then just after cache
disabled, the value was gone.
BRANCH=none
BUG=none
TEST=build and boot on mt8173-evb
Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff
Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee
Original-Signed-off-by: HC Yen <hc.yen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240323
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8799
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Allow read/write to registers at a given el. Also, make read/write
registers at current el call this newly added function.
BRANCH=none
BUG=none
TEST=build and boot on mt8173-evb
Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24
Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0
Original-Signed-off-by: HC Yen <hc.yen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240322
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8798
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The framebuffer structure lives in the coreboot tables. Those
tables have a checksum calculation applied over all the entries.
Therefore, one shouldnot be modifying fields within the coreboot
table entries because the calculated checksum would be wrong.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=On ryu, confirmed dev screen still works as well as cbmem utility
once booted.
Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16
Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230471
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8797
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Allocate noncacheable memory for frame buffer and save base
address to sys_libinfo.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed
Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226404
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This is important since mmu is disabled during the post_sysinfo_mmu_setup call
and calling printf can cause unaligned access.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt with console_init
Change-Id: I5ef72ee449fdcf30186f97485cc532d6c56b2c5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 688ef3856d0502d057c9543ee7763601156e6385
Original-Change-Id: Ie376e394d084edd6c999fc9edde79f15a0264e7b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222664
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8795
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Provide a function to obtain a new memrange with requested properties (type,
size, alignment, max_addr and other restrictions) from the set of available
memranges passed in coreboot table. One user of this function would be getting
memrange for dma, another one would be framebuffer.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: Ic5a63ca2dca6c71f4ca2d77e2e2c8180d32a38e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3cd75756e1405e044c029f2878bfcc9c8c962bdf
Original-Change-Id: I187d73a4d55d3c6f49afbe9852901672d25de8dc
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222110
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
1. keep functions and objects used entirely within mmu.c as static.
2. DMA region finding needs to terminate. Therefore, the next address
to be attempted needs to be less then the current end address.
3. Ensure mmu_ranges passed to mmu_init_ranges_from_sysinfo() has
0 entries marked as used.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Booted ryu with RAM hole above cbmem tables below 4GiB.
Change-Id: I71a9cb89466978aa63fca5d8bee97b8af75ea206
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 66518fd86e676bbddf52e9d9afdd76d72c8e2222
Original-Change-Id: I5cb4e5009359cb04c4e1b5fe60845f80fbdff02c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221725
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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