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path: root/payloads/libpayload/libc/coreboot.c
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2019-12-02lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot tableYu-Ping Wu
Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-03libpayload: refactor fetching cbmem pointersPatrick Georgi
There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-02libpayload: Add fmap_cache to sysinfo_tFurquan Shaikh
Now that FMAP is cached in CBMEM and its pointer is added to coreboot table for quick lookup, this change adds a new member "fmap_cache" to sysinfo_t that can be used by payloads to get to FMAP cache. BUG=b:141723751 Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-07-23vboot: deprecate vboot_handoff structureJoel Kitching
vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23coreboot_tables: pass the early_mmc_wake_hw status to payloadBora Guvendik
Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19vboot: make vboot workbuf available to payloadJoel Kitching
Create a new cbtable entry called VBOOT_WORKBUF for storing a pointer to the vboot workbuf within the vboot_working_data structure. BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14cbmem: rename vdat to chromeos_acpiJoel Kitching
There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07libpayload: Add SKU ID coreboot table supportJulius Werner
This patch adds support to read the SKU ID entry from the coreboot table that was recently added in coreboot. Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22743 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07libpayload: Minor board ID / RAM code cleanupsJulius Werner
This patch mirrors recent cleanups in coreboot regarding the strapping ID entries in the coreboot table. Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13libpayload: Add VPD address into lib_sysinfoKan Yan
BUG=chrome-os-partner:56947 TEST=Verifed country code can be parsed from VPD in depthcharge. BRANCH=None Change-Id: I2fbbd4a784c50538331747e1ef78c33c6b8a679b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acea6e2a200e8bd78fd458255ac7fad307406989 Original-Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/425819 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-07-31libpayload: Drop superfluous "continue"Patrick Georgi
Change-Id: I5a1d1ce8ba268b08d1275f392f0b9e602860c6ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260729 Reviewed-on: https://review.coreboot.org/15957 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Omar Pakker
2016-03-15libpayload: Drop CONFIG_LP_CHROMEOSStefan Reinauer
This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSCAaron Durbin
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information exported in the coreboot tables as the cpu_khz frequency. That allows get_cpu_speed() not to be called which currently relies on the 8254 PIT. As certain x86 platforms allow that device to be optional or turned off for power saving reasons, allow a path where get_cpu_speed() is no longer called. Additionally, this approach also allows the libpayload to not duplicate logic that already exists in coreboot. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Confirmed in payload TSC frequency is honored instead of using get_cpu_speed(). Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13671 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2015-07-14libpayload: store boot media information in sysinfoPatrick Georgi
Write boot media information in sysinfo, if it exists. This allows picking the right CBFS for further files in case there are several. Change-Id: I75a8ee6b93f349b9f2fab1e82826aba675949c0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23libpayload: Parse MTC and fill mtc_start and mtc_sizeFurquan Shaikh
Parse coreboot table and fill in mtc_start and mtc_size values in sysinfo structure. BUG=chrome-os-partner:41125 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: If210ea0a105f6879686e6e930cb29e66bc5e6cd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b70d0d35c85fa1a2317b0239276d5d9e7a550472 Original-Change-Id: I60b6f8ed4c704bd5ad6cce7fce2b9095babe181e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276778 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10563 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-22libpayload: cros: add serial number from coreboot tableStephen Barber
Add serial number to lib_sysinfo from coreboot table. BRANCH=none BUG=chrome-os-partner:37813 TEST=ryu boots and /proc/device-tree/firmware/android is populated with "compatible", "hardware", and "serialno" properties Change-Id: I565b332a16b177c51907ffab7976ebd7a665aaaf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5535119f5d499b04bdc178c3040241d2872c4e13 Original-Change-Id: Ie2e222780d1577689a1cbf76ae8514c74fc469f4 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/259140 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: Take flash parameters from corebootDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: Add RAM code to sysinfo_tDavid Hendricks
This adds CB_TAG_RAM_CODE and an entry to sysinfo_t. BUG=chrome-os-partner:31728 BRANCH=none TEST=Built and booted on pinky w/ depthcharge patch and saw that /proc/device-tree/firmware/coreboot/ram-code contains correct value Change-Id: I35ee1bcdc77bc6d4d24c1e804aefdbbfaa3875a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca6d044f2e719ded1d78a5ab3d923e06c3b88d6b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I69ee1fc7bc09c9d1c387efe2d171c57e62cfaf3f Original-Reviewed-on: https://chromium-review.googlesource.com/231132 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8755 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: Add support for parsing RAMOOPS range from corebootFurquan Shaikh
CQ-DEPEND=CL:228856 BUG=chrome-os-partner:33676 BRANCH=None TEST=Compiles and boots to kernel prompt. ramoops console log verified after causing kernel to fault. Change-Id: I5af9b995113ee30ac60347acba8fa945fb5cd17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 80c843fc78b137eb5540f8fefc4a69545b896fb6 Original-Change-Id: I8886015977e1fd999ef74fe73d08cff935cbce5c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/228742 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: make wifi calibration table available through sysinfoVadim Bendebury
The WiFi calibration blob saved in the CBMEM by coreboot needs to be visible by depthcharge to supply it to the kernel. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none yet Change-Id: I43a857f073a47ca315d400df4c53d5eb38e91601 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46a649608e6740e07c562c722fadd8c64e264b5f Original-Change-Id: Iecd8739c9269b58064b3c3275f5376cebcd6804b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225506 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8753 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-20libpayload: move MRC processing to x86 path and remove ACPI_GNVS duplicationVadim Bendebury
It turns out that CB_TAG_ACPI_GNVS is handled in both x86 specific and common coreboot table parsing code. The MRC cache case used only by x86 is handled in the common code. This patch restores sanity and moves processing to where it belongs. BRANCH=none BUG=none TEST=verified that arm and x86 targets build. Change-Id: Iaddaa3380725be6d08a51a96c68b70522531bafe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0afae893d5027026cb666cd46e054aeae4e71f83 Original-Change-Id: I2c114a8469455002c51593cb8be80585925969a7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225457 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20libpayload: cros: include mac addresses in coreboot tableVadim Bendebury
Pass MAC addresses found in coreboot table into lib_sysinfo. BUG=chrome-os-partner:32152 TEST=with all changes in place MAC addresses are properly inserted into the kernel device tree. Change-Id: I6b13c1c2c246362256abce3efa4a97b355647ef8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2fe74f86b4ed43eb8a3c9d99055afc5d6fb7b78 Original-Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219444 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20libpayload: Consolidate coreboot table parsingVadim Bendebury
There are three instances of coreboot.c in libpayload. for x86, arm and arm64 architectures. The arm and arm64 instances are exactly the same. The differences with the x86 instance are as follows: - a very slightly different set of coreboot table tags is parsed (one tag added and two removed) - instead of checking a fixed address if it contains the coreboot table, the x86 version iterates over two address ranges. This patch refactors the module, leaving architecture specific processing in arch subdirectories and moving the common code into libc. BUG=none TEST=none yet Change-Id: I1c7ad6f74e3498e93df78086ba0ff708c08e0a5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3df209d58ebd5c5b1cf0168f6466e065d1ef3598 Original-Change-Id: I6dfed73f6ba5939f692d0f98d2774c0e0312a25f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210770 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8750 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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