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2015-04-08arm: Dump additional fault registers in abort handlersJulius Werner
Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19libpayload: Add support for memory barriersFurquan Shaikh
Add support for memory barriers in arch {arm,arm64,x86}. This is required to force strict CPU ordering. Definitions are based on FREEBSD atomic.h definitions. BUG=chrome-os-partner:31533 BRANCH=None TEST=Memory barriers tested with ehci driver on arm64 Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552 Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213916 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8731 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-12libpayload: Expand setbits_le32() and fix readl() const-nessJulius Werner
setbits_le32() is not really arch-specific... the arch-specific part of accessing memory is wrapped by readl() and writel(), and the endianness can be accounted for with the right macros. Generalize the definitions, add a be32 version and move them to endian.h so that all platforms can use them. Also include endian.h from libpayload.h so we won't update any payload's old use of the macros (endianness is something useful enough to always have avalable anyway, and shouldn't clash with other things). This also fixes a bug where these macros would only be available if libpayload-config.h had been independently included before. Also fix a bug with readl() macros on all archs where they refused to work on const pointers (which they should). CQ-DEPEND=CL:208712 BUG=None TEST=Stuff still compiles. Built and booted on Storm. Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208713 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8 Reviewed-on: http://review.coreboot.org/8129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-01-09libpayload: Rework exception hook interfaceJulius Werner
This patch makes some slight changes to the exception hook interface. The old code provides a different handler hook for every exception type... however, in practice all those hook functions often need to look very similar, so this creates more boilerplate than it removes. The new interface just allows for a single hook with the exception type passed as an argument, and the consumer can signal whether the exception was handled through the return value. (Right now this still only supports one consumer, but it could easily be extended to walk through a list of hooks if the need arises.) Also move the excepton state from an argument to a global. This avoids a lot of boilerplate since some consumers need to change the state from many places, so they would have to pass the same pointer around many times. It also removes the false suggestion that the exception state was not global and you could have multiple copies of it (which the exception core doesn't support for any architecture). On the ARM side, the exception state is separated from the exception stack for easier access. (This requires some assembly changes, and I threw in a few comments and corrected the immediate sigils from '$' to the official '#' while I'm there.) Since the exception state is now both stored and loaded through an indirection pointer, this allows for some very limited reentrance (you could point it to a different struct while handling an exception, and while you still won't be able to return to the outer-level exception from there, you could at least swap out the pointer and return back to System Mode in one go). BUG=chrome-os-partner:18390 TEST=Made sure normal exceptions still get dumped correctly on both archs. Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202562 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> *** Squashed to prevent build failures. *** libpayload: align arm64 with new exception handling model The exception handling was previously updated, however the arm64 changes raced with hat one. Make the arm64 align with the new model. Without these changes compilation will fail. BUG=None BRANCH=None TEST=Can build libpayload for rush. Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204402 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e Reviewed-on: http://review.coreboot.org/8117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06libpayload: Introduce bit manipulation macrosVadim Bendebury
Some drivers being ported to depthcharge use io bit manipulation macros. The libpayload include file seems the most appropriate place to keep these macros in. There is no common io.h file across architectures, the x86 version could be added later if required. BUG=chrome-os-partner:27784 TEST=observed ipq806x SPI driver deptcharge port (WIP) compile properly. Original-Change-Id: I33f3be072faefce293c871f7e3bc3b2e6bc38ffe Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202559 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit ad18a605b4d0ec3251c1614e7358b42aa6b5c45a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8656e12af20ce4cf11d771942e8fe7d4eb2a560d Reviewed-on: http://review.coreboot.org/8062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-09ARM: API to Map Physical Address to Wipe Memory above 4GBDaisuke Nojiri
TEST=Booted nyan in normal and recovery mode. Created a map, filled it with some chars, then verified they can be read from the pointer returned. BUG=chrome-os-partner:25587 BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id1f1be4f6d2d5734d87bf3452d4806d0fe3fda88 Original-Reviewed-on: https://chromium-review.googlesource.com/188894 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 7fda3885f51c8d383585a80e99ab3df9c789d872) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6255d11396c87f40b0ae12ceab0fd152f2478529 Reviewed-on: http://review.coreboot.org/7658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09libpayload: ARM: Keep track of the CPSR when exceptions happen.Gabe Black
Use the SPSR to extract and inject CPSR values when an exception happens and pass that information to exception hooks. The register structure GDB expects when using its remote protocol has a spot for the CPSR. BUG=None TEST=Built and booted on link, nyan. BRANCH=None Original-Change-Id: Id950fb09d72fb0f81e4eef2489c0849ce5dd8aca Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/180253 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8e7014f24a580f84c91fa7b0369dfa922918adcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I49357fb6a65edeff7a9a48d54254308a6b0efdb7 Reviewed-on: http://review.coreboot.org/7657 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09libpayload: Make it possible to install callbacks for particular exceptions.Gabe Black
To support a GDB stub, it will be necessary to trap various exceptions which will be used to implement breakpoints, single stepping, etc. BUG=None TEST=Built and booted on Link with hooks installed and saw that they triggered when exceptions occurred. Built and booted on nyan. BRANCH=None Original-Change-Id: Iab659365864a3055159a50b8f6e5c44290d3ba2b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/179602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db0897b1ddad600e247cb4df147c757a8187626) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e7f724b99988cd259909dd3bd01166fa52317ec Reviewed-on: http://review.coreboot.org/7656 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
This patch changes the ENTRY() macro in asm.h to create a new section for every assembler function, thus providing dcache_clean/invalidate_all and friends with the same --gc-sections goodness that our C functions have. This requires a few minor changes of moving around data (to make sure it ends up in the right section) and changing some libgcc functions (which apparently need to have two names?), but nothing serious. (You may note that some of our assembly functions have data, sometimes even writable, within the same .text section. This has been this way before and I'm not looking to change it for now, although it's not totally clean. Since we don't enforce read-only sections through paging, it doesn't really hurt.) BUG=None TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not output into any binary anymore since no one actually uses it. Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/183891 (cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9 Reviewed-on: http://review.coreboot.org/7451 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09arm: Thumb ALL the things!Julius Werner
This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). BUG=None TEST=Snow and Nyan still boot. Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182212 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Conflicts: payloads/libpayload/include/arm/arch/asm.h src/arch/arm/Makefile.inc src/arch/arm/armv7/Makefile.inc *** There is an issue with what to do with ramstage-S-ccopts, and *** will need to be covered in additional ARM cleanup patches. Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-22arm: Update mem* functions to newer versionsJulius Werner
The memcpy/memset/memmove assembly implementations have been taken from U-Boot, which originally got them from Linux. I turns out that they are actually not that bad, but they could use an update. This patch pulls in the current Linux upstream versions of those files, removing some old U-Boot cruft such as checking whether the two pointers in a memcpy() are equal (really now?) or side-stepping the R8 register because it was used for special purposes. It also returns to the good old Linux ENTRY/ENDPROC macros since we have them now anyway, and straightens out the W() macro in preparation for unified thumb support. Change-Id: I138af269b423bef0a237759ac29f1ee58ca206a0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182179 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 777127997bde5785b21d422d0b6eb04c4328b478) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6918 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22arm: Move libgcc assembly macros to arch/asm.hJulius Werner
libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-15libpayload: x86: Add support for catching processor exceptions.Gabe Black
This functionality is already available for ARM, so lets add it to x86 as well. We'll want to be able to hook exceptions when running as a remote GDB target. Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179601 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6898 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 12:47:42 +0000