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Add error handling on I8042_CMD_WR_CMD_BYTE failure.
BUG=b:145130110
TEST=Draillion keyboard is usable on every boot.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I56c472ae7e399d4862c6e41b70f53a21d718157d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Wilco device uses the AT translated keyboard and doesn't need to set
scancode set. Remove the ignore flag and put into translation mode
instead.
BUG=b:145130110
TEST=Draillion keyboard is usable on every boot.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie1053e24e44c5bad28b56cc92d091e24f3d9b6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).
Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some special keys emit a prefix scan code 0xE0. We will ignore all
these except for the power button, F12 and cursor keys on drallion.
Media key mapping is set in depthcharge and will be sent to libpayload
keyboard driver. Whichever board requires this change will update its own
media key mapping.
BUG:b:139511038
TEST=boot in recovery mode, press F12 to go to diagnostic mode and power
button to confirm. Also in recovery mode left arrow, right arrow, up arrow,
down arrow changes the language on the firmware screen.
Change-Id: I1c11939d18391bebe53ca21cf33a096ba369cd56
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36654
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When the first CSW transfer failed, get_csw function will retry
CSW transfer again, but the return value is not updated.
Change-Id: I289916baa08d0a189d659164a0002347f6f435db
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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In interactive payloads, the USB stack's poll procedure is implicitly
called from the UI loop. Since all USB control transfers are handled
synchronously, polling hubs with these slows the UI significantly down.
So switch to interrupt transfers that are done asynchronously and only
perform control transfers when the hub reported a status change.
We use the interrupt endpoint's max packet size instead of the theo-
retical transfer length of `(bNrPorts + 1) / 8` as Linux' code mentions
hubs that return too much data.
Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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USB 3.1 GEN2 report speed type 4, add into speed enum.
BUG=b:139787920
BRANCH=N/A
TEST=Build libpayload and depthcharge on sarien and boot with
USB GEN2 HUB with USB disk. Check ultra speed device in cbmem log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia0ef12b2f0d91bf0d0db766bbc9019de1614a4f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35023
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We're planning to have a use case with a custom USB device that
implements the USB mass storage protocol on its bulk endpoints, but does
not have the normal MSC class/protocol interface descriptors and does
not support class-specific control requests (Get Max LUN and Bulk-Only
Reset). We'd like to identify/enumerate the device via
usb_generic_create() in our payload but then reuse all the normal MSC
driver code. In order to make that possible, this patch factors a new
usb_msc_force_init() function out of usb_msc_init() which will
initialize an MSC device without checking its descriptors. It also adds
some "quirks" flags that allow devices registered this way to customize
behavior of the MSC stack.
Change-Id: I50392128409cb2a879954f234149a5e3b060a229
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some broken USB mass storage devices send another zero-length packet at
the end of the data part of a transfer if the amount of data was evenly
divisible by the packet size (which is pretty much always the case for
block reads). This packet will get interpreted as the CSW and screw up
the MSC state machine.
This patch works around this issue by retrying the CSW transfer when it
was received as exactly 0 bytes. This is the same mitigation the Linux
kernel uses and harmless for correctly behaving devices. Also tighten
validation of the CSW a little, making sure we verify the length before
we read any fields and checking the signature in addition to the tag.
Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34485
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sometimes the display native orientation does not match the device
default orientation, so allow rotation of the framebuffer before
it is displayed on screen.
set_pixel now take coordinates in the rotated coordinate system,
and converts the coordinates before writing to the framebuffer.
Also, screen.size now matches the rotated system (_not_ the
framebuffer size).
BUG=b:132049716
TEST=Boot krane, see that FW screen is orientation properly.
Change-Id: If9316c0ce33c17057372ef5995a2c68de4f11f02
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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depthcharge prefers knowing where its input comes from
BUG=b:137378326
BRANCH=none
TEST=ctrl-d / enter to enter dev-mode works now.
Change-Id: I74b5be18c3583be17c73950ced93fad883690090
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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A typo introduced in commit bf2c693f893ab6f9458f1a4840c2a9cbbd4bb9f2
made the driver not build: DWC_SLEEP_TIME_US instead of
DWC2_SLEEP_TIME_US.
Change-Id: I197b25fd4f568cce7a4bbcee8cc285b25b26afb1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Increase the timeout for USB requests to 5 seconds for all USB host
controllers.
Prior to this fix, the xCHI driver was detecting false timeouts during
SET ADDRESS requests when nested downstream hubs were connected to the
xHCI root hub.
BUG=b:124730179
BRANCH=sarien
TEST=Build libpayload and depthcharge on sarien/arcada.
TEST=Without change replicate USB set address timeouts in depthcharge
when dock and 4K monitor connected (which includes a total of 4 USB
hubs). With timeout fix, depthcharge boots OS with no USB errors and
the same USB topology. Note that this tests xHCI operation only.
Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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calculate_color() uses the 'fbinfo' global that is initialized by
cbgfx_init(), so we need to run the latter before we can run the former
or we get a null pointer access.
Change-Id: I73ca8e20ca36f64d699379d504fd41dc2084f157
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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UART RX needs to be re-initialized in libpayload
as it is getting reset at the end of coreboot.
Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add error messages for all failed commands in keyboard_init().
Change-Id: Ie42ccbc4d850912c83e00376b27f192d5b652057
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Documentation is scarce on the matter, however the related coreboot
code suggests that after the ACK, the keyboard also sends the result
of the self test (passed/failed). It looks like this result is never
consumed here, probably resulting in further confusion for later com-
mands.
Let's revert this for now (if it's not too late for the 4.10 release)
and break things later again. IMHO, due to the fact that there are
dozens of different keyboard controller and keyboard implementations
and no accurate specification followed, such changes should be tested
on a lot of hardware before merge.
This reverts commit a99ed13e3397bc536012120aab8cadb827913863.
This reverts commit 7ae606f57f0b3d450ae748141b0e2367041b27d3.
Change-Id: I4d4304d5d8a01e013feac61016c59bcaeea81140
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Kepplinger <martink@posteo.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=build
Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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CB:32951 ("libpayload: Reset PS/2 keyboard") added a call to reset
keyboard and check the return value of keyboard_cmd() to compare
against I8042_KBCMD_ACK. However, keyboard_cmd() already checks for
ACK and returns 1 or 0 based on whether ACK is received.
This change fixes the check introduced by CB:32951 to compare against
0 just like the other checks for keyboard_cmd(). Additionally, it adds
error messages for all failed commands in keyboard_init() to make the
prints consistent in case of failure.
BUG=b:134366527
TEST=Verified that logs do not contain "ERROR: Keyboard reset failed"
anymore.
Change-Id: Idcadaae12e0a44e404a1d98c6deb633d97058203
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Reset keyboard controller to fix qemu make scan codes.
Change-Id: I5f8ad2d4be4b9e89d9af3a62726259e77f0403c1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Loading a libpayload based payload like coreinfo or FILO from SeaBIOS or
GRUB pressing keys does not give the expected results.
For example, pressing F1 gives the character 24 translated to scan code
6a. ESC for example 43 (111) in coreinfo loaded from SeaBIOS on QEMU
Q35.
The problem is not reproducible using the payload directly, that means
without SeaBIOS or GRUB. The problem seems to be, that those have already
initialized the PS/2 controller and AT keyboard.
Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to
be reset. That seems to fix the issue, when the keyboard was initialized
before.
TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary
payload. Run
qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio
press 3 to select the coreinfo payload, and verify that the keys F1 and
F2 are working.
Same with coreinfo loaded from GRUB on the ASRock E350M1.
Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Free several resources when AHCI initialization fails. Note that it is
only safe to free resources when the command engine has stopped, since
otherwise they may still be used for DMA.
Found-by: Coverity CID 1260719, 1260727, 1261090, 1261098
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6826d79338b26ff9696ab6ac9eb4c59f734687d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Ctrl-delete does nothing, so it falls through to the default case.
Add a comment to make this explicit.
Found-by: Coverity Scan #1260878
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Depthcharge uses the keyboard type to help determine whether
it can trust the keyboard for security-sensitive confirmations.
Currently it trusts anything except usb, but now there's a need
to distrust ec-based ps/2 keyboards that are associated with untrusted
ECs. To help facilitate this, coreboot needs to report more
details about non-usb keyboards, so this change replaces the current
instances of unknown with enum values that distinguish uart and gpio
from ec-based keyboards.
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash to systems with trusted and non-trusted
ECs. Confirmed that security confirmation can't be performed via
keyboard on a system with an untrusted EC but can still be performed
on a system with a trusted EC.
Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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GPT4 is a 32-bit timer and the counter of GPT4 will overflow in about
330 seconds (0xffffffff / 13MHz). Timer and delay functions will not
work properly if the counter overflows. To fix that we should use the
64-bit timer (GPT6).
BUG=b:80501386
BRANCH=none
Test=emerge-elm coreboot; emerge-kukui coreboot
Change-Id: I9f080e47253a1b1bab4636a45cb86c8666a25302
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
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set_option_with() expects a buffer of the exact size of the option.
Change-Id: I21332394f88cf2daa4f733a544627d6d3c6ef26c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iee244d0cd7d64934fbfc34778a45e21e97646628
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The firmware is basically ignoring F11 and F12 without this change.
BUG=b:130143385
TEST=local compile and flash to device. Confirmed that press of F11 and F12
keys now generates appropriate keypress events (and the same codes that
are already generated by these keys on an external USB keyboard).
Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Found-by: Klockwork
BUG=NONE
TEST=Boot to OS on GLK Sparky
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d4636f0429de829e746909492c2f543026a02ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Cast cpu_khz to a 64 bit integer to prevent possible
integer overflow (the multiplication is currently done
using 32 bit math). Similar to 61dac13 (libpayload:
timer: cast cpu_khz to make sure 64bit math is used).
Found-by: Coverity Scan, CID 1261177
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Iadb0abb7c7cc078f31a6d88d971f5d1b8ac62a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch is a raw application of
find payloads/ -type f | \
xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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If a PS/2 AUX device is not present then the AUX test command
during i8042_probe() will time out and add ~500ms to the boot time.
In order to avoid this only test the PS/2 AUX port if
CONFIG_LP_PC_MOUSE is enabled.
BUG=b:126633269
TEST=boot on device without AUX port and check that this command
does not get executed, saving ~500ms at boot.
Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If keys are pressed at boot some keyboard controllers will not
properly respond with an ACK to commands, which results in the
keyboard_init function aborting before it adds the keyboard to the
input device list.
This same keyboard controller will manage to properly return keyboard
data when keys are pressed later, so it is possible for it to be
functional in the payload even if it does not respond properly to
every command during initialization.
In order to allow payloads to use the keyboard when this happens a
new Kconfig option is added to ignore the keyboard ACK response and
always add the keyboard to the input device list. This option is
disabled by default and must be enabled by the specific boards that
need it.
BUG=b:126633269
TEST=boot on device with this controller and press keys during boot
and see that the keyboard is still functional in the payload.
Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
console->scroll_up() was hanging when console->rows is 0. This
was happening on delan if no screen was attached. If there are no
rows, just return.
BUG=b:119234919
TEST=Boot delan with no flat panel. System boots to OS
Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This patch removes several timer and serial drivers (and configs) that
were specific to platforms which have been dropped in coreboot.
Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. In this particular
situation, dev->buf is already pointer to u8, and there's no need to convert
to void *.
BUG=b:118484178
TEST=Build libpayload.
Change-Id: Ib70b8ce11abc88c35be4092f097cfff385921f46
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Fill reg_base with physical register base address.
Tested on Lenovo T500.
Change-Id: If42135c8e10b70d5ac9626521abd9cca3cf40053
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18600
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For debugging purposes always set the pciaddr attribute.
Tested on Lenovo T500.
Change-Id: I83a0e7f7196ed251fa0becc4e56bef3ca68f20f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Don't leak buffers on device detach.
Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
-device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
-device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd
Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Exit on first sucessful CONTROL transfer instead of doing
GET_DESCRIPTOR_TRIES iterations.
Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
-device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
-device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd
Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
|
|
BUG=none
TEST=compiled on grunt and made sure USB still works in depthcharge
Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.
BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.
Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Make it obvious that the command has failed.
BUG=b:76831439
TEST=Verified on grunt
Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.
Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.
BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.
Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This makes it easier to know what offset each register references.
BUG=b:76831439
TEST=none
Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This change ensures that keyboard scanning is disabled and keyboard is
set to default state while disconnecting the keyboard. This is
required to ensure that the controller doesn't keep scanning and
buffering keystrokes which could lead to OS drivers reading stale
data.
BUG=b:110024487
TEST=Verified that kernel driver is able to probe correctly even if
multiple keys are pressed during handoff from payload to OS.
Change-Id: I1ffb8904d545284454c1825ee2e7c0087fc13762
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This change adds macros for commands (written to 0x64) and keyboard
commands (written to 0x60) for 8042 controller.
BUG=b:110024487
Change-Id: I74b2388d048e35b5bdf5bd862d0975e88f1bd6af
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add function to get active keyboard modifiers.
Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18601
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new method to retrieve active usb keyboard modifiers.
Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18602
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
keyboard_getchar();
BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang
Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Make use of i8042 driver to add PS2 mouse driver support.
Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.
Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Make use of i8042 driver in keyboard.c.
Required to add PS/2 mouse support.
Tested on Lenovo T500.
Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move keyboard.c into i8042 folder.
Change-Id: Idd30a9082e48a451d9fe5ead3f3dda4e6396b50c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18595
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.
Required to support PC keyboard and PC mouse at the same time.
Tested on Lenovo T500.
Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie1da925aceb01c2d21b472bf171000803004578f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Uses ARCH64 Timer
TEST=build
Change-Id: Ic312bcf3bc7e80482b7f038e2dbc4abaaffd5956
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Change-Id: Ib90564e32f5ff204aa5d856024b7eed2624a77b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.
Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Make is so that a different timer source can be provided instead
of TSC on x86 platforms.
BUG=b:72378235,b:72170796
Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I9645d76d05014722e4ae0c398d82f7f8e34d6f1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
libpayload needs a static copy of the out of line function
`font_glyph_filled()` in every TU that needs it. So make it static
inline.
This fixes a build error by gcc (Debian 7.1.0-12) 7.1.0 from Debian
Sid/unstable. This happens with any libpayload based payload like
coreinfo, nvramcui or tint.
```
[…]
LPCC build/coreinfo.elf (LINK)
/src/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(corebootfb.libc.o): In function `corebootfb_putchar':
/src/coreboot/payloads/libpayload/drivers/video/corebootfb.c:173: undefined reference to `font_glyph_filled'
[…]
```
Change-Id: I931f0f17b33abafdc49aa755a0dad65e28820750
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This introduces support for font scaling with a factor provided via
Kconfig. In practice, the font itself is not scaled at any point in
memory and only the logic to determine whether a pixel should be filled
or not is changed.
Thus, it should not significantly impact either the access time or
memory use.
Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This introduces helpers for accessing the included font, instead of
using hardcoded values provided by the font's header itself.
It will allow painlessly adding support for font scaling in a subsequent
change. It should not introduce any functionality change.
Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
AHCI spec explicitly states that we may poll.
TEST=Ran FILO on kontron/bsl6 and observed that the controller
always becomes ready during the first delay.
Change-Id: If34694abff14d719d10d89bc6771dbfa12065071
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This is (thankfully) not done by coreboot any more for recent chipsets.
Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add a driver to handle multiple low level mouse drivers
and provide basic cursor acceleration support.
Tested on Lenovo T500.
Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20396
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Iee8dc03d5a4ca7537c7da4fed2c67b169c9e2422
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Change-Id: I0347594e9480dedc4845b6863733a67fc5e47e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20371
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Id4892adba161cd08eecde71a011384b6c465b98f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
If the framebuffer address is zero the corebootfb_init() function
should abort and not attempt to use it for video, otherwise it
will likely hang.
This was tested by booting on a board that does not have a display
attached and includes the previous patch to zero the framebuffer
structure in the coreboot tables.
Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
CQ-DEPEND=CL:506453
Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
cbgfx currently does not support portrait screen which height >width.
so add it.
Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19474
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
This patch allows the CBMEM console to persist across reboots, which
should greatly help post factum debugging of issues involving multiple
reboots. In order to prevent the console from filling up, it will
instead operate as a ring buffer that continues to evict the oldest
lines once full. (This means that if even a single boot doesn't fit into
the buffer, we will now drop the oldest lines whereas previous code
would've dropped the newest lines instead.)
The console control structure is modified in a sorta
backwards-compatible way, so that new readers can continue to work with
old console buffers and vice versa. When an old reader reads a new
buffer that has already once overflowed (i.e. is operating in true ring
buffer mode) it will print lines out of order, but it will at least
still print out the whole console content and not do any illegal memory
accesses (assuming it correctly implemented cursor overflow as it was
already possible before this patch).
BUG=chromium:651966
TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco.
Also confirmed correct behavior across suspend/resume for the latter.
Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When console input driver registers itself, perform flush of input
buffer to avoid interpreting any stale key presses before libpayload
is run.
keyboard.c: Remove the redundant buffer flush.
8250.c: Ensure that serial_hardware_is_present is set before call to
add input driver.
BUG=b:37273808
TEST=Verified that any key presses in serial console before payload is
up do not have any effect after the payload starts running.
Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.
Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.
Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19279
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.
BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.
Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Power button events are usually dropped because the button is not in
the keyboard matrix range. Add condition to forward it like other keys.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot and make sure power button selection
in depthcharge's detachable menus is processed on reef.
Change-Id: I86897fa8d73a56533ef62bba05458ac3d339237e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25654e214f0ab8685d445ced62612a02be851126
Original-Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/428199
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087
Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/426338
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18125
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I1308bdca90f1a09d980f384ee85552198a39b965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260940
Reviewed-on: https://review.coreboot.org/18036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia163872846906c6c78144a984a405812f856f626
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1325835
Reviewed-on: https://review.coreboot.org/18035
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Iaf84de2330b433076a66c22fa72ffb45e957c0dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1261177
Reviewed-on: https://review.coreboot.org/18034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This fixes the generic timer driver to get the current tick from the
high register, so that comparison with the high count value (obtained
previously from the same register) has a chance to succeed.
Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Coverity considers this a copy&paste error, and maybe it is. In any
case, it makes sense to check the variable that (if the condition is
true) is changed, and the values are the same before that test, so the
change is harmless.
Change-Id: I163c6a9f5baa05e715861dc19643b19a9c79c883
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347376
Reviewed-on: https://review.coreboot.org/17837
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ie8ca342a32323be4c26c236a5209052ec724317f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Chrome OS builds always have some inherent differences to "standard"
libpayload configurations: they don't want to use curses or things like
storage drivers, they always use the coreboot framebuffer and USB, etc.
This patch reintroduces CONFIG_LP_CHROMEOS as an option that only
affects Kconfig defaults. This allows Chrome OS builds to select most of
what they need in one go and reduces board-specific .config files to
only the options that are really specific to that board.
Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on
x86 boards, which probably makes sense for all of libpayload (some but
far from all ARM boards use 8250-compatible UARTs, and we should
probably not default a platform option unless it's going to be correct
with very high probability).
BRANCH=None
BUG=None
TEST=Built and booted Jerry and Oak.
Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: e558f59
Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently every non-x86 platform supported by libpayload needs to
provide its own timer driver. Most of the ones we have accumulated there
look almost identical: For the frequency, return a preset constant. For
the value, read a 32-bit register, possibly read another 32-bit register
and shift+OR it with the previous one, then return that.
Let's replace this with a single .c file that can easily handle all of
those cases. Menuconfig convenience can still be maintained by providing
several presets that select different defaults for the driver's
configuration options (register address(es) and frequency).
Removes an "enabled" check from Samsung MCT driver since coreboot always
unconditionally enables that timer anyway.
CQ-DEPEND=CL:344809
BRANCH=None
BUG=None
TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s
Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: a036af6
Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347749
Reviewed-on: https://review.coreboot.org/17023
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Testing: booted successfully.
Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
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Move the configuration of the timer, storage and USB drivers from the
main Kconfig to three separate ones stored in the respective
directories.
This reduces the LOC of Kconfig and makes it more manageable.
Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15914
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This removes the newlines from all files found by the new
int-015-final-newlines script.
Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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cbgfx currently makes a separate function call (recomputing some values)
for every single pixel it draws. While we mostly don't care that much
about display speed, this can become an issue if you're trying to paint
the whole screen white on a lowly-clocked Cortex-A53. As a simple
solution for these extreme cases, we can build a fast path into
clear_screen() that just memset()s the whole framebuffer if the color
and pixel format allow it.
BUG=chrome-os-partner:54416
TEST=Screen drawing speed on Kevin visibly improves (from 2.5s to 3ms).
Change-Id: I22f032afbb86b96fa5a0cbbdce8526a905c67b58
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15524
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
add a memory barrier before ringing the doorbell, to ensure
all TRB changes are written to memory.
BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform
Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c21e92
Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/346831
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15111
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none
Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb
Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333304
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:49249
TEST=Compiles and boots and detect USB storage
BRANCH=none
Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3
Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333311
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There is a lot of generic code in the 8250 driver that should
be available for non-8250 systems with serial ports as well.
Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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