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2022-11-21libpayload: Fix compiler warningsThomas Heijligen
Following warnings occur when compiling with `i386-elf-gcc (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0` drivers/serial/8250.c:75: [-Werror=unused-variable] Move variable declaration inside the `#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block drivers/udc/dwc2.c:505: [-Werror=format=] use `%zd` to match type `size_t` Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69764 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-21payloads: Drop unneeded empty linesElyes HAOUAS
Change-Id: I6faeb7c783052edc4217d2d301dbb905e1fc6a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-24libpayload: Cache physical location of serial-console structNico Huber
In the presence of self-relocating payloads, it's safer to keep physical addresses in `libsysinfo`. Change-Id: Icd30e95c6b8115d16dd793914fb01a1a9da1854f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20libpayload: Make 8250 UART driver relocation safeNico Huber
`lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Accessing the wrong value during relocation of FILO resulted in a hang with DEBUG_SEGMENT and UART console enabled. Work around that by caching the whole table entry locally. An alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reto Buerki <reet@codelabs.ch> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09libpayload: Add uart/serial driver support for trogdorT Michael Turney
Change-Id: I5be3904298cd88c60dbc6d8d662beeede2abe442 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35960 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17payloads: Fix typosElyes HAOUAS
Change-Id: Ib7f1ba1766e5c972542ce7571a8aa3583c513823 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-26libpayload/serial/qcs405: Mark uart console as suchPatrick Georgi
depthcharge prefers knowing where its input comes from BUG=b:137378326 BRANCH=none TEST=ctrl-d / enter to enter dev-mode works now. Change-Id: I74b5be18c3583be17c73950ced93fad883690090 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-27libpayload: Re-initialize UART RXPrudhvi Yarlagadda
UART RX needs to be re-initialized in libpayload as it is getting reset at the end of coreboot. Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04libpayload: Add UART for qcs405Prudhvi Yarlagadda
TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-13libpayload: classify all keyboardsMatt Delco
Depthcharge uses the keyboard type to help determine whether it can trust the keyboard for security-sensitive confirmations. Currently it trusts anything except usb, but now there's a need to distrust ec-based ps/2 keyboards that are associated with untrusted ECs. To help facilitate this, coreboot needs to report more details about non-usb keyboards, so this change replaces the current instances of unknown with enum values that distinguish uart and gpio from ec-based keyboards. BUG=b:129471321 BRANCH=None TEST=Local compile and flash to systems with trusted and non-trusted ECs. Confirmed that security confirmation can't be performed via keyboard on a system with an untrusted EC but can still be performed on a system with a trusted EC. Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-07payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find payloads/ -type f | \ xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-05libpayload: Remove unused timer/serial driversJulius Werner
This patch removes several timer and serial drivers (and configs) that were specific to platforms which have been dropped in coreboot. Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/30029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2017-04-19libpayload/libc/console: Flush input driver buffer on initFurquan Shaikh
When console input driver registers itself, perform flush of input buffer to avoid interpreting any stale key presses before libpayload is run. keyboard.c: Remove the redundant buffer flush. 8250.c: Ensure that serial_hardware_is_present is set before call to add input driver. BUG=b:37273808 TEST=Verified that any key presses in serial console before payload is up do not have any effect after the payload starts running. Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19345 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09libpayload: ipq40xx: Introduce timer and uart driverVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16libpayload: Split off generic serial API from 8250 driverStefan Reinauer
There is a lot of generic code in the 8250 driver that should be available for non-8250 systems with serial ports as well. Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14371 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09libpayload: use 32bit access when accessing 4byte wide uart registersPatrick Georgi
This fixes serial on rk3288. Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13636 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-28libpayload: Remove redundant 8250 MMIO32 UART driverAlexandru Gagniuc
The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10libpayload: Fix merge of PL011 UART supportNico Huber
Wished I hadn't seen that. Git saw the conflict (file was gone), both committer and reviewer thought it would be a good idea to re-add it as dead code (see 558e9b5: libpayload: Add minimal support for PL011 UART). Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-21cygnus: enable serial driver for depthchargeDaisuke Nojiri
BUG=chrome-os-partner:35807 BRANCH=broadcom-firmware TEST=tested input and output by the cli in depthcharge Change-Id: Icd517a366a3fe5bdcf9e9aeb4284d7e4378ee3f2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 02c3b6c82d9d71beb19a0879591c754fa7685362 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200568 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Scott Branden <sbranden@broadcom.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I97144fc6f19969b8cf3872939c9c74efaef3604b Original-Reviewed-on: https://chromium-review.googlesource.com/256413 Reviewed-on: http://review.coreboot.org/9844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17purin: add basic set of files for libpayloadDaisuke Nojiri
BUG=none BRANCH=tot TEST=emerge-purin libpayload depthcharge coreboot chromeos-bootimage Change-Id: I6a46067a288ecea352a2724c62c62066e3f4a383 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 355371317dde0546fbab2cd109bc17463f77c4fd Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I8c43acc4d270c3b2d7c18af07c077a553e3c6f6f Original-Reviewed-on: https://chromium-review.googlesource.com/245492 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: read register width from coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32Julius Werner
We have two drivers for a 100%-identical peripheral right now, mostly because we couldn't come up with a good common name for it back when we checked it in. That seems like a pretty silly reason in the long run. Both Tegra and Rockchip SoCs contain UARTs that use the common 8250 register interface (at least for the very basic byte-per-byte transmit and receive parts we care about), memory-mapped with a 32-bit register stride. This patch combines them to a single 8250_mmio32 driver (which also fixes a problem when booting Rockchip without serial enabled, since that driver forgot to check for serial initialization when registering its console drivers). The register accesses are done using readl/writel (as Rockchip did before), since the registers are documented as 32-bit length (with top 24 bits RAZ/WI), although the Tegra SoC doesn't enforce APB accesses to have the full word length. Also fixed checkpatch stuff. A day may come when we can also merge this driver into the (completely different, with more complicated features and #ifdefs) 8250 driver for x86 (which has MMIO support for 8-bit register stride only), both here and in coreboot. But it is not this day. This day I just want to get rid of a 99% identical file without expending too much effort. BUG=None TEST=Booted on Veyron_Pinky and Nyan_Blaze with and without serial enabled, both worked fine (although Veyron has another kernel issue). Change-Id: I85c004a75cc5aa7cb40098002d3e00a62c1c5f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7959c19356d2922aa414866016540ad9ee2ffa8 Original-Change-Id: Ib84d00f52ff2c48398c75f77f6a245e658ffdeb9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225102 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08libpayload: Add drivers for bg4cdDaisuke Nojiri
BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13libpayload: ipq808x: stale interrupt shall not be cleared unconditionallyYogesh Lal
The serial driver hangs in cases when FIFO has more than single word to be processed. Easiest way to reproduce is to paste a string of greater than 4 characters in cli. Clearing the RXSTALE interrupt without draining all the characters from FIFO leads to the issue as the driver is dependent on msm_boot_uart_dm_read function to reinitialize for next transfer. Logically the driver is organized in such a manner that next transfer never gets initiated till rx_data_read < total_rx_data. Clearing the RXSTALE without consideration of total number of characters (or words) unprocessed makes the msm_boot_uart_dm_read to return on the first if conditional. Thus the driver is stuck forever. A quick fix is to avoid clearing the stale interrupt. Reset is handled whenever a new transfer is initialized in msm_boot_uart_dm_init_rx_transfer. BUG=chrome-os-partner:29542 TEST=manual -Paste a string greater than 4 characters in cli. Original-Change-Id: I016afb01a77cd14764f0176f6bf144fb29796c2f Original-Signed-off-by: Yogesh Lal <ylal@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209512 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 61528884ad2c0a8e146054bbfeb01a3bc73b9692) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I936af5daa52a25f62133bdf9fb44f0b68cf34e88 Reviewed-on: http://review.coreboot.org/8667 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-12libpayload: Add Rock Chip drivershuang lin
Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-09libpayload: Fix baseaddr access in serial/tegra.cFurquan Shaikh
Fix baseaddr typecast to allow use in 32- and 64-bit systems BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie5ded744d75a0ae4d1428d04ff2478bdfe54d146 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204424 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b56814fe5fc7d3a2fdfb324d4baafb27a9d3ffd6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icedc1c819e39b92a0dd92e98f848e15b3039dfbe Reviewed-on: http://review.coreboot.org/8123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06libpayload: ipq808x: introduce uart driverVadim Bendebury
This adds a UART driver for the ipq8064 controller. It still does not quite work in the receive direction - the receive FIFO returns read data in 32 bit chunks, which means that 4 keys need to be pressed before a character pops out of the driver (and it reports it as a single character). This issue is being addressed separately, the driver is being checked in to facilitate concurrent development. BUG=chrome-os-partner:27784, chrome-os-partner:29313 TEST=with deptcharge modifications in place, the AP148 board comes up to the depthcharge prompt: Starting depthcharge on storm... Original-Change-Id: Ief2cfcca73494be5c4147881144470078adcefb8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202045 Original-Reviewed-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 4499318fb9a4e663c504d7c41380ccf2aa89da29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e07d7568c20c0e570222971ff219de3a6d9b7cc Reviewed-on: http://review.coreboot.org/8061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-22libpayload: console: Allow output drivers to print whole strings at onceJulius Werner
The console output driver framework in libpayload is currently built on the putchar primitive, meaning that every driver's function gets called one character at a time. This becomes an issue when we add drivers that could output multiple characters at a time, but have a high constant overhead per invocation (such as the planned GDB stub, which needs to wrap a special frame around output strings and wait for an acknowledgement from the server). This patch adds a new 'write' function pointer to the console_output_driver structure as an alternative to 'putchar'. Output drivers need to provide at least one of the two ('write' is preferred if available). The CBMEM console driver is ported as a proof of concept (since it's our most performace-critical driver and should in theory benefit the most from less function pointer invocations, although it's probably still negligible compared to the big sprawling mess that is printf()). Even with this fix, the problem remains that printf() was written with the putchar primitive in mind. Even though normal text already contains an optimization to allow multiple characters at a time, almost all formatting directives cause their output (including things like padding whitespace) to be putchar()ed one character at a time. Therefore, this patch reworks parts of the output code (especially number printing) to all but remove that inefficiency (directives still invoke an extra write() call, but at least not one per character). Since I'm touching printf() core code anyway, I also tried to salvage what I could from that weird, broken "return negative on error" code path (not that any of our current output drivers can trigger it anyway). A final consequence of this patch is that the responsibility to prepend line feeds with carriage returns is moved into the output driver implementations. Doing this only makes sense for drivers with explicit cursor position control (i.e. serial or video), and things like the CBMEM console that appears like a normal file to the system really have no business containing carriage returns (we don't want people to accidentally associate us with Windows, now, do we?). BUG=chrome-os-partner:18390 TEST=Made sure video and CBMEM console still look good, tried printf() with as many weird edge-case strings as I could find and compared serial output as well as sprintf() return value. Original-Change-Id: Ie05ae489332a0103461620f5348774b6d4afd91a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196384 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ab1ef0c07736fe1aa3e0baaf02d258731e6856c0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I78f5aedf6d0c3665924995cdab691ee0162de404 Reviewed-on: http://review.coreboot.org/7880 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09libpayload: serial: Move the depthcharge serial drivers into libpayload.Gabe Black
These drivers need to be ready right away and never really fit into the depthcharge driver model anyway. CQ-DEPEND=CL:194063 BUG=None TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze, and daisy. BRANCH=None Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194057 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93 Reviewed-on: http://review.coreboot.org/7224 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
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