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path: root/payloads/libpayload/arch/mips
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2015-07-06cbfs: define libpayload_init_default_cbfs_media weaklyDaisuke Nojiri
To allow a payload to define its own libpayload_init_default_cbfs_media, default implementation needs to be defined weakly. BUG=none BRANCH=tot TEST=dumped a cbfs file from depthcharge cli on jerry Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352 Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283061 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30libpayload: Make Kconfig bools use IS_ENABLED()Stefan Reinauer
This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_LP_.+?)\b,if IS_ENABLED\($1\),g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_LP_.+?)\b,if !IS_ENABLED\($1\),g' `find . -name *.[ch]` Change-Id: Ib8a839b056a1f806a8597052e1b571ea3d18a79f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10711 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-12libpayload: Rename Config.in -> KconfigStefan Reinauer
libpayload is the only Kconfig based project under the coreboot umbrella that is using Config.in as its name for Kconfig config files. Rename that to Kconfig as on the other projects for consistency. Change-Id: I1c69ec13582d88409384b492484535dcc5e1ad20 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-22libpayload: fix a mips memmove() bugVadim Bendebury
size_t is an unsigned type and as such is a bad choice for a counting down loop counter. BRANCH=all BUG=none TEST=editing cli command line does not cause hangs any more Change-Id: I0502553b5e2143052345edeb205a01558fccd9b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c171f739497fcd26589976676ab94b23cd7ee8b Original-Change-Id: I4aa38379ac356114fc91a32cced2fa45a00a09d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262714 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Tested-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21libpayload: mips: Do not set C0_EBase_WGAndrew Bresticker
The WG (write gate) bit in C0_EBase allows the upper two bits of the exception base address to be set to something other than 2'b10, thus allowing it to be relocated out of the traditional KSEG{0,1} range. Since we're not using the segmentation features introduced by EVA to relocate the unmapped segments, the exception vectors should remain in KSEG0. Don't set the WG bit so that the upper two bits of the exception base (2'b00, because of the identity mapping) are ignored and we execute the exception vectors out of KSEG0. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246697 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9822 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21libpayload: mips: Add macros to convert to/from KSEG{0,1} addressesAndrew Bresticker
Add helper macros to convert between physical addresses and KSEG{0,1} addresses. Also get rid of the virt_to_{bus,phys}_offset variables as these are fixed values. As nobody seems to be using getpagesize() on MIPS, no need to keep virtual.c. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: Ia26c8eae53eb8f860747a6b321363776841d1a94 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c422b02e9a2a20d130913b1cfb835ad74c39ddca Original-Change-Id: I9476cd225a08534830c700cba7bf9d3ef871757e Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247190 Reviewed-on: http://review.coreboot.org/9821 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21libpayload: mips: Use KSEG1 to access DMA-coherent memoryAndrew Bresticker
Use bus_to_virt() to convert the physical address of the DMA coherent region to an address in KSEG1 which is suitable for device memory accesses. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: If382feda66f6d829f8b3548ab263cf603cab2e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a88a175f6d6db81d3154fb5dd31a44363ab94653 Original-Change-Id: I9ad6435495df2c71d8f81a782f1c3dfcfd4aeb28 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246696 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9818 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21libpayload: mips: Set BASE_ADDRESS to 0Andrew Bresticker
Now that coreboot has identity-mapped DRAM, use base address 0 (KUSEG) instead of 0x80000000 (KSEG0). BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: I39845250a1b8cea6e5360efce16770751ffce13d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c1cbc1d7f6873c0be30d4206a2030f3b468acf24 Original-Change-Id: I76d98664f1bca73ae8acc9f545e68de9173c3cab Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246695 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: arch/mips: add virt/bus/phy_to_bus/phy/virt operationsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA and bring up board; works as expected BRANCH=none Change-Id: I368494f388b82969dda0ce73a38824791efce616 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e4c2bbcbdbcf706062724cffe2d5f15953468ace Original-Change-Id: Id5c9b1d65c6ec87f2aba06995dc940c50afb041f Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245386 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: mips: add SOC CPU frequencyIonela Voinescu
Add CPU frequency corresponding to SOC. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected. BRANCH=none Change-Id: I05458070a15c6cf1ef0fc2104715a63902a38887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4afe332bcc41afeb7e31e918e345c3336f7dc604 Original-Change-Id: I55b788faf7984bafc2509cac69867a772c7cb863 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241427 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload: mips: add memcmp to the MIPS string functionsIonela Voinescu
The default string functions work with multiple of 4 bytes (sizeof(unsinged long)); MIPS will use LW/SW instructions for these operations and if the source and destination addresses are not aligned it will trigger an exception. Therefore, this implementation does all data access operations per byte, because there is no guarantee that the provided strings are properly aligned. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; behaves as expected BRANCH=none Change-Id: I05b43673deb954f022d12cb9c3d7baac26be2a34 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e13b3d31726404abd8c8e5c8780d3d3e16e032d Original-Change-Id: I456e312eb6b7fee2eff10e461af7f578aed07648 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241885 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-21libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu
Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 15:06:29 +0000