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Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/beechnutcity CRB
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com>
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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which is based on Intel Sapphire Rapids Scalable Processor chipset
which was product launched on Jan. 10 2023.
The site-local/* files are Intel binaries that are not published yet
but coreboot build validation system would skip these binaries when
they are in "site-local" directory.
Please make sure you have the correct Intel binaries for your AC CRB
and place them to the right location accordingly.
CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is
LinuxBoot payload, there are several ways to build it, one way is to
build it from the x86_64 qemu example from osf-builder:
git clone https://github.com/linuxboot/osf-builder
cd examples/qemu; make kernel
commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support)
would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to
enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in
your defconfig.
Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Otherwise configurations in src/mainboard/ocp/tiogapass/Kconfig
cannot be selected by
make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass
Change-Id: I88d5619269a6a9c09e84061642206a17c91db042
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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OCP Delta Lake is developed and validated against LinuxBoot payload.
Need to put the respective binary blobs in site-local/deltalake to
build the final coreboot image.
Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline,
CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is
the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4
is for a faster boot time.
Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS.
Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm
is present in devicetree.cb it is necessary to always include
the driver in the build.
Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
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OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.
The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.
TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 52
On-line CPU(s) list: 0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:
0:1st timestamp 28,621,996
40:device configuration 178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: I2a2de7ccb96996211c45da3f9ec9bf6f71cc0c89
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Add config file that can be used to build a fully working
Tioga Pass image.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Ifff3591ef9fff40117c60e85900bde9c3729bd94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Removes the pre-defined VGA bios file and id because
the build system includes every vgabios.
Also make the VGA output primary by default
Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18181
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The coreboot builder makes use of the pre defined configuration
files by executing abuild with -d option. These configuration
files contain a basic configuration.
Change-Id: I41470fe7aaa0fdae545ad9d702326a202d0d2312
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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