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2023-07-03Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cseMatt DeVillier
Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flashMichał Żygowski
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-11Append per-board ccache statistics in logKyösti Mälkki
Starting with ccache 4.4 it is possible to collect statistics about cache miss/hit rates in a separate file. Add the info of the build at end of created make.log file or on stdout. Change-Id: I1bab712712f4d6379ec6733fdc55b234e3845da7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75087 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31Makefile.inc: Create function to add a file to CBFSMartin Roth
This function can be called to more easily add a file to CBFS. Additional file attributes can be added later: cbfs-files-y += pagetables pagetables-file := $(objcbfs)/pt pagetables-type := raw pagetables-compression := none pagetables-COREBOOT-position := $(CONFIG_ARCH_X86_64_PGTBL_LOC) becomes $(call add-cbfs-file-simple, pagetables, $(objcbfs)/pt, raw, none ) pagetables-COREBOOT-position := $(CONFIG_ARCH_X86_64_PGTBL_LOC) This is especially useful inside macros where you may want to add an unknown number of entries. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I72bb2f21fb22f650b7970c7a37a48c10a4af0ed5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-31Makefile.inc: Remove duplicated -Wreturn-type optionElyes Haouas
"-Wall" turns on "-Wreturn-type". Change-Id: Iad4d8465112e3ca89d7d78e391d52c2b2d5f37cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-14Makefile.inc: Warn about set but unused variables with GCCArthur Heymans
Clang was already warning about this. Synchronize the behaviour between both compilers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3331a7437b17ab5ac97cef94511bb29c020bdff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75032 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-04Makefile.inc: introduce all_x86 targetFelix Held
For compilation units that should be built for all stages that run on the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP which is an ARM core, the 'all' target can't be used, since that would result in the compilation unit also being added to the verstage target in the verstage on PSP case. In order to not need to add a compilation unit to the 'bootblock', 'verstage_x86', 'romstage', and 'ramstage' targets in separate lines in the Makefile, introduce the 'all_x86' target that adds a file to 'bootblock', 'verstage_x86', 'romstage', 'postcar', and 'ramstage'. The compilation units also need to be added to the 'postcar' stage which is only present on the pre-Zen SoCs to be able to also use the 'all_x86' target in common AMD code that is also used in those pre-Zen SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74150 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-28util/ifdtool: Add option to create FMAP templateMaximilian Brune
On systems that do not provide their own *.fmd (Flashmap) file, we fall back to a default flashmap file. That file however does not contain the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap. It can therefore easily happen that the placement of the blobs collides with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough). The fmaptool can't catch that, since it does not know of the blobs placement. This patch basically maps the regions described in the IFD (Intel Firmware Descriptor) to the default Flashmap. Test: Build and see that build/fmap.fmd contains all blobs now (on intel systems that are supported by the ifdtool) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82cb252fff456773af69943e188480a4998736fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-17Makefile.inc: fix multiple jobs build issueMichał Żygowski
Certain C source files for coreboot stages require fmap_config.h to be present. When building coreboot using multiple jobs the dependency is not always satisfied due to race condition and results in make error. Work around it by adding fmap_config.h to stage C deps. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a70beedf2eb1c018c5ff98163904253f9a87a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69819 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-03-13top/Makefile.inc: Define regions-for-file with a flexibilityZheng Bao
If we need to put a CBFS chunk into a specific region, add a line in any Makefile.inc regions-for-file-xxx=region_name TODO:Do a complete binary identical test for all the mainboards. Change-Id: Ie37a8a9230dc8b8e5664be8806f047afb94fba69 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-10top/Makefile.inc: add _tohexZheng Bao
Get string of hex value of a given number. Change-Id: I6d3525db19089938897b9d19ad9875bb07e0eecf Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-05Makefile.inc: Use 'Wmissing-include-dirs' command optionElyes Haouas
This is to warn if a user add to Makefile a path to nonexistent directory. Change-Id: I5a30c3830f30509deaaadc6eaeab0e17bc08565c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70251 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-23makefile: Add $(objutil)/kconfig/conf as make dependencyLean Sheng Tan
This patch fixes the build failure with 'make -j' where the build fails at "$(MAKE)... savedefconfig" as that rule doesn't have the dependency on kconfig/conf. Normally make takes care of all dependencies, so parallel builds work well. However if you have recursive make calls, i.e. make calling make like in these recipes, there is no single make with a global view of the dependencies anymore, and then multiple "makes" can try to build the same file concurrently. Adding that explicit dependency on build/util/kconfig/conf makes sure the recursive make is only called later when the top-level make already finished building build/util/kconfig/conf. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id44ab44618b0ddfb3c2472c469499429118bf76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72070 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-01-08Kconfig: Add option to compress ramstage with LZ4Martin Roth
When ramstage is loaded asynchronously, as on the skyrim boards, the faster decompression of LZ4 allows for faster boot times than the tighter compression of LZMA. To make this change, the name of the existing ramstage_compression option needs to be updated. BUG=b:264409477 TEST=Boot skyrim, look at boot speed Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07build: Combine "savedefconfig" and "stripped config" in CBFS `config`Julius Werner
The intention of CB:69710 was that the expanded config file introduced there would be a strict superset of the old version and could be used in all the same cases. This is generally true except for a small oversight: if a boolean Kconfig is `default y`, but was manually set to `n` by the user, the new `config` file does not include a line for it. Running `make olddefconfig` on such a file will again introduce the option as `y`. It turns out that `make olddefconfig` actually parses those "load-bearing comments" in that case. This patch fixes the problem by also generating the minimal defconfig (like before CB:69710), and then just appending the non-comment lines from the full config that don't appear in it already. This ensures that any "load-bearing comments" in the defconfig remain in the file and the result of Kconfig utilities regenerating a full config from there will again be the same as before CB:69710. In addition, it clearly separates the "minimal defconfig" part of the file from the rest, making it easy for people to extract that if they need it; while also keeping all the config values in one file to make it easy to grep for a certain value. Also eliminate that random backslash in the recipe that doesn't seem to have any good reason to exist and was probably a typo to begin with. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I52ba5d20d3536498fae79d529acf7135f97ef1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-06src/ec/intel: Create common code for board_id implementationHarsha B R
This patch creates initial common code structure for board_id implementation for intel rvp platforms. Board_id helps in identifying the platform with respect to CHROME_EC and INTEL_EC (Windows_EC). Changes include 1. Create initial board_id.c and board_id.h 2. Modify the Makefile to include src/ec/intel directory BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-05Makefile.inc: Use 'Wold-style-definition'Elyes Haouas
Warn when a definition is using '()' instead of '(void)'. Use of ‘()’ is considered an old-style definition in C1x standards, but probably not in C2x. Change-Id: I734cfffe3e89996ab13e846cc08e13753f24f742 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18build: List all Kconfigs in CBFS `config` file, compress itJulius Werner
The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can remove all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-18Makefile.inc: Remove workaround ACPI warningsArthur Heymans
No boards now have a missing dependency so remove the workaround. Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69514 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06Makefile.inc: Fix build hang if file-size is run on empty stringMartin Roth
Currently, if for some reason, the file-size command is called on an empty string, the build will hang waiting for stdin input to cat. Since wc accepts a file, this cat was unnecessary anyway. Put the file name in quotes so an empty string will result in calling wc on an actual null file instead of just leaving the filename blank. This results in an error, and will probably halt the build. BUG=214790407 TEST=Build default build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I3dacf1968ed897a8ebd00f95583c2f254a7fb55a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-22Add SBOM (Software Bill of Materials) GenerationMaximilian Brune
Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-02Makefile.inc: Disable compiler warning array-compare for GCCPaul Menzel
gcc 12 fails the build with the warning below: CC romstage/lib/cbfs.o src/lib/cbfs.c: In function 'switch_to_postram_cache': src/lib/cbfs.c:31:32: error: comparison between two arrays [-Werror=array-compare] 31 | if (_preram_cbfs_cache != _postram_cbfs_cache) | ^~ src/lib/cbfs.c:31:32: note: use '&_preram_cbfs_cache[0] != &_postram_cbfs_cache[0]' to compare the addresses Instead of following gcc’s suggestion, disable the warning for gcc as requested by Julius [1]: > Can we just set -Wno-array-compare instead? There's nothing illegal > about that expression and as we can see in this case, there are > perfectly reasonable cases where you might want to do something like > that. On the other hand, I don't really see a realistic scenario where > this warning could prevent a real problem (anyone who doesn't know > that array1 == array2 doesn't compare the array elements in C > shouldn't have any business submitting code to coreboot). [1]: https://review.coreboot.org/c/coreboot/+/62827/1 Found-by: gcc-12 (Debian 12-20220313-1) 12.0.1 20220314 (experimental) [master r12-7638-g823b3b79cd2] Found-by: gcc (Debian 12.1.0-7) 12.1.0 Change-Id: I322f7cc57dcca713141bddaaaed9ec034898754d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14Makefile.inc: objcopy extracts a wrong section of cbfs_master_headerPetr Cvek
Commit 75226bb879837 ("Makefile.inc: Generate master header and pointer as C structs") may cause objcopy to copy a wrong section of object file resulting in miscompiled image with missing CBFS master header. This makes the usage of secondary payloads impossible. For example a wrong section for CONFIG_ANY_TOOLCHAIN + objcopy 2.38-slack151 will copy ".note.gnu.property". This patch constraints the sections to .data and .bss only. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I1b9a73ece7067c9c5100cb294775078f838e263b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-06Makefile.inc: Update submodules only when git is presentMartin Roth
Instead of trying to update the submodules, then skipping each update if git is not present, just don't try to update the submodules at all. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I83ef48a21820c0983e38823331c9ba0fe0fc277f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-06Makefile.inc: Notify about updating submodulesMartin Roth
There is no longer any information printed when updating submodules, so on the initial build, this can lead to a long delay without explaining what's going on. Just add an information line that the submodules are being updated so that the user can see what's happening. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I987e50b99e39b976bc8367525549153e1eba69cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-07cbfstool: Expand CBFS verification validity checkJulius Werner
This patch adds a new line to `cbfstool print -v` output that records the overall CBFS verification health of the image. While this info was already visible from individual fields before, it's nice to have a one-stop location to see "this is a good image" without having to carefully parse a lot of output manually. Also add a few lines to the Makefile that check whether this field is valid for the final image (it always should be, but hopefully this check will allow us to catch regressions like the one fixed by CB:64547 sooner in the future). BUG=b:233263447 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-27Makefile.inc: Add bootblock to CBFS before othersYu-Ping Wu
With CBFS verification, cbfstool (CB:41121) needs bootblock to be present in coreboot.pre in order to locate the metadata hash stored in it. Therefore we have to ensure that bootblock is added to CBFS before other CBFS files are added. To solve the problem, create the 'add_bootblock' function, and call it in the coreboot.pre recipe. Because bootblock.bin is now a prerequisite of coreboot.pre, it will get built even if CONFIG_BOOTBLOCK_IN_CBFS=n. BUG=b:233263447 TEST=emerge-guybrush coreboot TEST=emerge-corsola coreboot chromeos-bootimage TEST=cbfstool image-kingler.bin print -v TEST=Kingler booted successfully BRANCH=none Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-12Makefile.inc: Remove leftoverArthur Heymans
Commit 9a8d0a03db (crossgcc: Upgrade IASL from 20211217 to 20220331) removed this parameter. Change-Id: Iba062efcabac88edc1f7937b75ea9d5d884b448b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-12Makefile.inc: Add x86 bootblock as a separate targetArthur Heymans
Some platforms don't need a top aligned bootblock in cbfs like Intel APL or modern AMD platforms as the bootblock is loaded differently. So they don't need the top aligned cbfs bootblock. To not clutter the main make file move out adding the bootblock. Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12Makefile.inc: Move adding bootblock on non-x86 targetsArthur Heymans
This can be done in a separate Makefile target. Change-Id: I50eae4f00d171d26a221ca969086f4f294fa524b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-12Makefile.inc: Generate master header and pointer as C structsArthur Heymans
The makefiles don't like cbfs file names with spaces in them so update the file name with '_' instead of spaces. To keep the master header at the top of cbfs, add a placeholder. This removes the need to handle the cbfs master header in cbfstool. This functionality will be dropped in a later CL. On x86 reserve some space in the linker script to add the pointer. On non-x86 generate a pointer inside a C struct file. As a bonus this would actually fix the master header pointer mechanism on Intel/APL as only the bootblock inside IFWI gets memory mapped. TESTED on thinkpad X201: SeaBIOS correctly finds the cbfs master header. Change-Id: I3ba01be7da1f09a8cac287751497c18cda97d293 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-20Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct generationArthur Heymans
There is no easy way to add dependencies to cbfs-structs objects and fmap_config.h is a generated file. Follow-up commits depend on it being available so add it in the cbfs-struct makefile function. Change-Id: I7067ff144d38c1ff058825819419b2a2e7801e17 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-08IASL: Correct warning message for IASL missing dependencyFrans Hendriks
Warning for _SRS includes _SRS. Warning for _DIS includes must have _SRS twice. Remove requirement _SRS for _SRS is present. Removed second _SRS for _DIS is present. BUG=N/A TEST=Verify correct message on built of facebook FBG1701 Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Signed-off-by: Frans Hendriks <fhendriks@eltan.com>´ Reviewed-on: https://review.coreboot.org/c/coreboot/+/63250 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-04crossgcc: Upgrade IASL from 20211217 to 20220331Elyes Haouas
"REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is not needed any more as it’s included upstream. Changes: https://acpica.org/node/199 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-31Makefile: Clean up old targetsArthur Heymans
Some of these targets seem to come from a long time ago. Now just rm -rf $(obj) is all that is needed for a clean. Change-Id: Iccc62b3c54ee2a074c25674715403c1457f6aad3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-30Makefile.inc: Explicitly delete coreboot.preRaul E Rangel
coreboot.pre doesn't follow the standard Make conventions. It gets modified by multiple rules, and thus we can't compute the dependencies correctly. This means we need to manually delete it before starting the dependency calculations. i.e., Building firmware with the seabios payload now works correctly. Fixes: dd6efce934f ("Makefile: Add .SECONDARY") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-25$top/Makefile.inc: Move common folder before other sibling onesZheng Bao
Putting src/soc/*/common before src/soc/*/*, and src/superio/common before src/superio/*,(which is already moved but with duplicated folder "common") can make the variables in common Makefile get the expected value before they are used in other subdirs. The later "*" also contains "common", which needs to be eliminated by "filter-out". Then we can put some common variables from all the subdir Makefile.inc to the common Makefile.inc to reduce code redundancy. Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-28Makefile: Add a build target for .mapRaul E Rangel
We don't currently have a build target defined for .map files. This means they can't be used as a dependency. This change splits the .map creation into its own rule. BUG=b:221231786 TEST=Build guybrush and verify .map still exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1ce21902e97390aa9520670299ef08debf4458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/62399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28IASL: Ignore IASL's "Missing dependency" warningElyes HAOUAS
IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects: 1) If _PRS is present, must have _CRS and _SRS 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) 4) If _SRS is present, probably should have a _DIS (Remark only) IASL will issue a warning for each missing dependency. Ignore this warnings for existing ASL code and issue a message when the build is complete. Change-Id: I28b437194f08232727623009372327fec15215dd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27Makefile.inc: Don't ignore IASL's "multiple types" warningElyes HAOUAS
Intel Lynx Point ASL code is fixed. So don't ignore "Multiple types (Device object requires either a _HID or _ADR, but not both)" warning. Change-Id: Ie9398879a76ad3d36454772a1c23da083af14b59 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-23Makefile.inc: Add `-fno-pie` to `ADAFLAGS_common`Paul Menzel
Building libgfxinit with Debian’s toolchain – latest test with *gnat-11* 11.2.0-13 from Debian sid/unstable – the build fails with the error below. E: Invalid reloc type: 10 E: Unable to create rmodule from 'build/cbfs/fallback/ramstage.debug'. Debian’s toolchain is built without enabling PIE by default. So, explicitly pass `-fno-pie` to `ADAFLAGS_common` to be independent from how the toolchain was built. TEST=*gnat* 11.2.0-13 successfully. builds purism/librem_cnl/variants/librem_mini with libgfxint. With the coreboot toolchain `make BUILD_TIMELESS=1` produces the same `build/coreboot.rom` for `BOARD_PURISM_LIBREM_MINI_V2=y` on top of commit 50251400d2 (sb/intel/common/firmware: Reword me_cleaner warning) with and without the change. Change-Id: I6661937906d95c130c6099f598d61b21e958fd85 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-10guybrush: Inject SPDs into APCBRob Barnes
Inject SPDs into APCB at coreboot build time. BUG=b:209486191 BRANCH=None TEST=Boot guybrush and nipperkin with injected APCB Change-Id: Ib21085855324e0d473dd5e258f35a52bed326901 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29acpi,Makefile: Add preload_acpi_dsdtRaul E Rangel
This will allow us to preload the dsdt.aml file. BUG=b:179699789 TEST=Build guybrush | 80 - write tables | 1.564 | 1.08 Δ( -0.48, -0.03%) | | 85 - finalize chips | 15.483 | 13.543 Δ( -1.94, -0.14%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibf69ecb947811a2eec861018e3ba5f858155f1c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22Makefiles: Hide skipping submodule info unless V=1Martin Roth
Currently, git prints out the submodules that are being skipped twice on many builds. This patch hides that output unless the build is set to show it with `make V=1`. This is the normal way of showing the extra information during the build. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7b5c7f1f79dcc88793a9a21f2e92e7accc5de1e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59511 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-16src/lib/prog_loaders: Add preload_ramstageRaul E Rangel
This will enable preloading ramstage. By preloading the file into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush to OS and see 12ms reduction in boot time. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-19util/cse_serger: Add a new tool for stitching CSE componentsFurquan Shaikh
This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19util/cse_fpt: Add a new tool for managing Intel CSE FPT binariesFurquan Shaikh
This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11Makefile: Add src/soc/* to subdirsFurquan Shaikh
This change adds src/soc/* to subdirs before src/soc/*/* to allow Makefile in src/soc/* to provide any common helpers that will be useful for any src/soc/*/*. This is done to primarily ensure that the helpers are defined before being invoked by the SoC Makefile.inc. This is utilized by Intel CSE stitching mechanism in following changes. BUG=b:189177580 Change-Id: I91579a87016fdc2b9ca2d798b81969c21c18b4a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-23build system: Deduplicate symbols in objdumpPatrick Georgi
New binutils versions automatically resolve references to debug symbol files and parse their content as well when objdump'ing data. This leads to multiple mentions of symbols, so deduplicate references. Change-Id: I5d597399c515904313ba36d7aab9178bc0dade14 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-22Makefile.inc: Replace linker flag -nostartfiles with --nmagicIru Cai
While the gcc(1) driver has the `-nostartfiles` option, ld(1), the program the coreboot toolchain uses to link the object files, doesn't have it. In binutils before 2.36, this option is interpreted as `-n -o startfiles`, in which the `-o` option is overridden by a later `-o` option, so only the `-n` option has effect, which is the `--nmagic` long option of ld(1). So the correct linker option in this place is `--nmagic`. It is tested that without `--nmagic`, ld can generate a much bigger x86_64 romstage, so this option is still needed. This error is found when trying to update binutils to 2.36 and later versions, where ld(1) is unable to disambiguate options and reports an error. Change-Id: I27dc2209abdc6fec866716a252736c5cf236a347 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-09Revert "Makefile.inc: Drop the cbfs master header from non-X86"Julius Werner
This reverts commit d109354c0f1d4b155c60701cd42e632213350d72. Reason for revert: Breaks libpayload CBFS code when accessing non-default CBFS. BUG=b:193093750 Change-Id: Id7f47406e6126f19e1fd6bc9d33c8c9d0cb9450d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-07-07Makefile.inc: Drop the cbfs master header from non-X86Arthur Heymans
The pointer to the header has a x86 top mmaped address even though the boot medium is not mapped that way. If no pointer is used to find the header FMAP is needed. If FMAP is used anyway there is no need for a cbfs master header. Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07Makefile.inc: Fix IFITTOOL dependenciesArthur Heymans
Add IFITTOOL as a dependency where needed and remove where it is unneeded. Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-07Makefile.inc: Remove explicit ramstage dependency for coreboot.romArthur Heymans
This is already handled in $(prebuild-files). Change-Id: I648f97198772d30d6d267ab9d6f7fa8d1d5d0e91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-18option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbolAngel Pons
Mainboards with variants may not always use the same cmos.layout file. Turn the hardcoded path into a Kconfig symbol to allow changing it. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom and with `USE_OPTION_TABLE` selected, building for the Asus P8H61-M PRO produces an identical coreboot image. Change-Id: I4cc622dcb70855c06cb8a816c34406f8421180df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54366 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18Makefile.inc: Drop unused `cbfs-files-processor-vsa`Angel Pons
VSA (Virtual System Architecture) is specific to AMD Geode CPUs, which are no longer supported in current coreboot. Drop this remnant. Change-Id: I28bf61cb953e3352b59aa91059341e4de8f84f23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-30Makefile,tests: Move cmocka checkout into top level MakefileRaul E Rangel
cmocka is currently ignoring the UPDATED_SUBMODULES flag. Move the cmocka checkout with the other submodule checkouts. BUG=none TEST=Make sure cmocka is not checked out if UPDATED_SUBMODULES=1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a1db809368a77d2c0f9c9a796d62555ec476dc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-03-27Makefile.inc: Use `additional-dirs` for $(objcbfs), $(objgenerated)Nico Huber
We use `additional-dirs` for a single `mkdir -p` invocation for all directiories. I don't see why these two, $(objcbfs) and $(objgenerated), should be an exception. Fixes clean builds for targets that don't include the phony `coreboot` target, e.g. `make qemu`. Change-Id: I85abaa74cddefd2bd669e2b5c8934352775070fe Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-17Makefile.inc: Don't compile bare structs with asan-global=1Arthur Heymans
This messes up the bare structs. Change-Id: I5a13bd9f4b11530a6dd5f572059fed851db44757 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18Makefile: Do not use GCC specific options with LLVM/clangPaul Menzel
Building with LLVM/clang (`COMPILER_LLVM_CLANG=y`), Debian clang version 11.0.1-2 fails due to unknown warning options. error: unknown warning option '-Wlogical-op'; did you mean '-Wlong-long'? [-Werror,-Wunknown-warning-option] error: unknown warning option '-Wduplicated-cond' [-Werror,-Wunknown-warning-option] As these are GCC specific, only add them, when building with GCC (and not scan-build). Fixes: 04e0712f46 ("Treewide: Add some gcc's warning options") Change-Id: I6190c1f3df97fb0be51f8dab7e1f5f2a033f5d86 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-12Makefile.inc: Don't ignore _HID & _ADR coexisting in Broadwell ASL codeElyes HAOUAS
Issue fixed in commit d152837 so don't allow use of _HID and _ADR at same time. Change-Id: I52beba66230a3542a7039f496b51be0aa4bdcce4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50384 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22Makefile.inc: Avoid --emit-relocs on RISC-VJulius Werner
There seems to be a bug[1] in the GNU linker for the RISC-V architecture triggered by symbols that are more than 2GB offset from the program counter. My next patch is introducing symbols like that and stuck on this problem. The code path that runs into the issue is only taken when passing the --emit-relocs flag, which is really only needed for building rmodules. Since RISC-V platforms don't use any rmodules at the moment, let's disable the flag on RISC-V until the issue can be fixed in the toolchain. [1]: https://sourceware.org/bugzilla/show_bug.cgi?id=27180 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I784a506034325c0ba937589416acaafbf80080e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49449 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12util/ifdtool: Add coreboot build system supportPatrick Georgi
When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-04drivers/vpd: Add VPD region to default FMAP when selectedMatt DeVillier
Currently, use of the VPD driver to read VPD tables from flash requires the use of a custom FMAP with one or more VPD regions. Extend this funtionality to boards using the default FMAP by creating a dedicated VPD region when the driver is selected. Test: build qemu target with CONFIG_VPD selected, verify entry added to build/fmap.fmd. Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-27src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23Makefile: Add $(xcompile) to specify where to write xcompileRaul E Rangel
This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-17arch/arm: Replace .id section with build_info in CBFSKyösti Mälkki
For arch/arm[64], the offsets to board identification strings and CONFIG_ROM_SIZE inside .id were never really used; it was only a convenience to have the strings appear near the start of image. Add the same strings in an uncompressed file in CBFS. Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11Makefile.inc: Remove the CBNT bootblock flagArthur Heymans
At the moment this was only used for aligning the bootblock to 64 bytes. At the moment this automatically done with CONFIG_C_ENV_BOOTBLOCK_SIZE. Change-Id: I0c879119e525b512eebe3f4c5ff9b2f426c6b6ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-09Makefile.inc: Fix empty output when processing C struct files in CBFSXi Chen
When passing $(@) to eval command, $(@) is replaced by empty string, Also, the $(@) in cbfs-files-processor-struct is a temporary file name, so we should quote it by an extra '$' or use the arg ($1 or $2) directly. For example: cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ # ** $(@) is empty string instead of $(2) ** printf " CC+STRIP $(@) \n"; \ # ** $(1) contains the name of source file ** printf " CC+STRIP $(1) \n"; \ ......) Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Id6a66e25d7dfe8fe6410e517593ed22a438d2f82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48201 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08Makefile: Allow platform to provide additional params for add cmdFurquan Shaikh
This change adds optional CBFSTOOL_ADD_CMD_OPTIONS that can be used by arch/SoC/mainboard Makefiles to supply any additional arguments that need to be passed into cbfstool when using cbfstool add command. This is useful when platform wants to add these parameters depending upon some arch/SoC/mainboard specific configs. Immediate use case is the fast SPI controller on Intel platforms adding arguments for extended window base and size. BUG=b:171534504 Change-Id: I2f48bc3f494d9a5da7e99b530a39d6078b4a881c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47884 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02lib/trace: Remove TRACE supportKyösti Mälkki
Looks like the option is generally not compatible with garbage collections. Nothing gets inlined, for example is_smp_boot() no longer evaluates to constant false and thus the symbols from secondary.S would need to be present for the build to pass even if we set SMP=n. Also the addresses of relocatable ramstage are currently not normalised on the logs, so util/genprof would be unable dress those. Change-Id: I0b6f310e15e6f4992cd054d288903fea8390e5cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-01Makefile.inc: Alloc .bss* sections for "struct" file typeYu-Ping Wu
When the global variable of a "struct" CBFS file is zero (for example, CB:47696), the binary will appear in the .bss* section in the ELF file (instead of .data). This results in an empty binary file added to CBFS, so that file size check will fail when reading it at runtime. BUG=b:173751635 TEST=emerge-asurada coreboot TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS BRANCH=none Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47903 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27Makefile.inc: Move adding mcu FIT entriesArthur Heymans
This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20Makefile.inc: Add CARRIER_DIR to component discoveryMaxim Polyakov
The idea is to split the “mainboard” category into “variants” and “carrierboards”, in the case when we use the COMe module together with the Carrier Board instead of a single monolithic motherboard. Previously, the “variants” category defined the type of motherboard, which has a number of differences from the base one, for example, it differed in the size or type of memory, and in the configuration of the interfaces. Thus, there is no need to create a separate directory in src/mainboard for a board that is similar in configuration to the base board. But for a COMe module, “variants” contains different variants of only this module, and the entire Carrier Board configuration is allocated to a separate category - “carrierboards”, and each of the variants can be used with one of the many boards in “carrierboards”. For example, in the case of the Kontron mAL10 COMe module, variant refers to the COMe-mAL10 or COMe-m4AL10 module type. They differ in the type of memory (DDR3L or DDR4), and maybe they differ in some chips (see more in https://www.kontron.com/products). However, all variants contain the same type of processor/SoC. The "carrierboards" directory can be able contain both the Kontron's Evalution carrier boards (such as Eval Carrier2 T10 and COMe Ref.Carrier-i T10 TNI) and third party vendor backplanes that are compatible with the COMe modules from “variants”. Thus, the src/mainboard/<module-name> directory contains the common configuration code for all variants from src/mainboard/<module-name>/ variants, which can be supplemented/redefined with a configuration from src/mainboard/<module-name>/carrierboard/<vendor-carrierboard-name>. This architectural solution will be able to systematize and simplify understanding of the code structure for COMe modules and will allow vendors to add/maintain their code in a separate directory. This work is also the first step towards to union of all carrierboards into the global category in src/carrierboard on a par with all boards from src/mainboard. The patch takes this into account in the build system and adds CARRIER_DIR component to use the “carrierboards” category, as it has done for VARIANT_DIR. TEST = Build ROM image for Kontron mAL10 COMe module together with T10 TNI carrier board (https://review.coreboot.org/c/coreboot/+/39133). Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16Makefile.inc: Move adding SeaBIOS cbfs config filesArthur Heymans
Using the INTERMEDIATE target this can be done in the proper dir. Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-10sec/intel/cbnt: Stitch in ACMs in the coreboot imageArthur Heymans
Actual support CBnT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46456 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04util/qemu: Add `qemu` make targetNico Huber
Add some mechanics to automatically have a `qemu` make target for supported configurations. So with a QEMU target selected in Kconfig, one would ideally only have to run `make qemu` to test things. There are some notable variables that can be set or adapted in `Makefile.inc` files, the make command line or the environment. Primarily for `Makefile.inc` use: QEMU-y the QEMU executable QEMU_CFG-y a QEMU config that sets the available default devices, used to run more comprehensive tests by default, e.g. many more PCI devices For general use: QEMU_ARGS additional command line arguments (default: -serial stdio) QEMU_EXTRA_CFGS additional config files that can add devices QEMU_CFG_ARGS gathers config file related arguments, can be used to override a default config (QEMU_CFG-y) Examples: $ # Run coreboot's default config with additional command line args $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso" $ # Force QEMU's built-in config $ make qemu QEMU_CFG_ARGS= Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-26sconfig: Split up sconfig-generated static.hTim Wawrzynczak
Currently sconfig generates a `static.h` to accompany `static.c`. However, some payloads may decide they would like to consume the FW_CONFIG macros as well. The current state of `static.h` makes this impossible (relying on `device/device.h`). This patch splits up `static.h` into 3 files: `static.h, `static_devices.h`, and `static_fw_config.h`. `static.h` simply includes the other two `.h` files to ensure no changes are needed to other code. `static_devices.h` contains the extern'd definitions of the device names recently introduced to sconfig. `static_fw_config.h` contains the FW_CONFIG_FIELD_* macros only, which makes it easily consumable by a payload which wishes to use FW_CONFIG. Also refactor the generation of all these output files, as the code was getting messy. Change-Id: Ie0f4520ee055528c7be84d1d1e2dcea113ea8b5f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie
The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09sconfig: Allow chipset to provide a base devicetreeDuncan Laurie
This change extends the devicetree override one more layer and allows the chipset to provide the base devicetree. This allows the chipset to assign alias names to devices as well as set default register values. This works for both the baseboard devicetree.cb as well as variant overridetree.cb. chipset.cb: device pci 15.0 alias i2c0 off end devicetree.cb: device ref i2c0 on end BUG=b:156957424 Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05amdfwtool: Clean up the Makefile of amdfwtoolZheng Bao
Add Makefile.inc to compliant with other tools. Makefile is kept for building amdfwtool by typing make in the folder. Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-18sconfig: Switch to getoptDuncan Laurie
Instead of positional arguments switch sconfig to use getopt and pass the arguments as options in the build system. This will make it easier to add additional options. Change-Id: I431633781e80362e086c000b7108191b5b01aa9d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31Makefile.inc: Print warning type ignored by IASLMaxim Polyakov
- Use a new variable to store the list of warning types; - print this list when building an image. TEST = build image on Kontron mAL-10 COMe module: IASL 3150 2158 3133 warning types were ignored! IASL build/dsdt.aml disassembled correctly. Change-Id: I46f761612254b400563f8567be9bd61601f23467 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-17Makefile.inc: Remove redundant warning flagElyes HAOUAS
'-Wstrict-aliasing' is turned on by '-Wall'. '-Wstrict-aliasing' is only active when -fstrict-aliasing is active, so add it. 'BUILD_TIMELESS=1' on gigabyte/ga-945gcm-s2l gives the same binary. Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44216 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24assert.h: Do not use __FILE__ nor __LINE__ on timeless buildsAngel Pons
When refactoring, one can move code around quite a bit while preserving reproducibility, unless there is an assert-style macro somewhere... As these macros use __FILE__ and __LINE__, just moving them is enough to change the resulting binary, making timeless builds rather useless. To improve reproducibility, do not use __FILE__ nor __LINE__ inside the assert-style macros. Instead, use hardcoded values. Plus, mention that timeless builds lack such information in place of the file name, so that grepping for the printed string directs one towards this commit. And for the immutable line number, we can use 404: line number not found :-) Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-06-30Add qc_blobs repositoryJulius Werner
This patch adds a separate blobs repository for Qualcomm blobs, analogous to the existing AMD blobs. Qualcomm's binary licenses allow files to be redistributed and used by anyone, but they explicitly require the user to agree to the license terms when just *downloading* the binary (even if they're not using them to build any firmware). Some community members do not like to have to agree to licenses for files they're not actually using, so we are keeping these files separate from the main blobs repository and adding an extra Kconfig to make sure the user is aware of and must explicitly agree to this before downloading these files. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-28Makefile.inc: Simplify fsp submodule checkAngel Pons
TEST=Building Asrock H110M using FSP from repo updates the submodule. Change-Id: I25023af88d878353a04db456009249da67e41521 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15arch/x86: Remove XIP_ROM_SIZEKyösti Mälkki
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27Makefile: Add missing APCB_EDIT_TOOL variableRaul E Rangel
Apparently I missed adding this variable definition. BUG=b:157140753 TEST=Build APCBs with clean tree :) Fixes: cbaa835f211 ("soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9055ed3507996cbf78687a97599aab3b0b39d6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41738 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22make: Add a target and dependency to parse the devicetree with sconfigDuncan Laurie
This change adds a target to the top level Makefile that allows building sconfig and generating static.c/static.h without building the rest of coreboot. It also adds $(DEVICETREE_STATIC_C) to the c-deps for each stage so the files are generated before the build runs. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I4320288422230d8913dfa7cc7b7512775a1a797b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41439 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09treewide: more SPDX header workPatrick Georgi
Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-20Makefile: Set FMAP size to 0x200 for non-x86 boards with default fmdFurquan Shaikh
This change updates FMAP_FMAP_SIZE for non-x86 boards using default fmd file to be 0x200 just like for x86 boards. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f58696b26fbb5363d67bec4056653da83485776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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