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2021-05-14Documentation/distributions: Order vendor list lexicographicallyPaul Menzel
Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-05-14Documentation/distributions: Separate all vendors by exactly one blank linePaul Menzel
Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-14Documentation/distributions: Separate parenthesis by dashesPaul Menzel
Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-13payloads/Tianocore: Update default build target, simplify build optionsMatt DeVillier
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig option since it applied only to CorebootPayloadPkg. Clean up the Makefile now that we're only building from a single Tianocore package/target. Test: build/boot qemu Q35 target with both UefiPayload and Upstream options. Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12Doc/nb/intel/sandybridge: Fix up some typos and cosmeticsAngel Pons
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-12Documentation/releases: Add more details about release notesPatrick Georgi
There are some steps when updating the release notes that are easily missed (see: I missed them for 4.14), so document them. Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation/releases: Add 4.15 release notes templatePatrick Georgi
Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation/releases: Update checklistPatrick Georgi
Since we want commits to go through 24 hours of review, move the vboot list update a week earlier. Also point more directly at the right script to execute. Change-Id: I49e6dfe22894402d5a0526588f8a04595ac88862 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12Documentation: Update vboot support listPatrick Georgi
Created by util/vboot_list/vboot_list.sh Change-Id: I49536c26540c0fd1940a32f588fa49afb55b108a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-11docs: add recommendation for gpios regarding soft strapsMichael Niewöhner
Soft straps, that can be configured by the vendor in the Intel Flash Image Tool (FIT), can influence some pads' default state. It is possible to select either a native function or GPIO mode for some pads on non-server SoCs, while on server SoCs most pads can be controlled. Thus, add a recommendation to always configure all pads for a board to guarantee integrity between different board or vendor firmware revisions where the soft straps might have been changed. Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-11docs: correct and rewrite documentation regarding n/c / unused padsMichael Niewöhner
Intel PDGs starting from Skylake / Sunrise Point state that, different from the general recommendation in digital electronics, unconnected GPIOs defaulting to GPIO mode do explicitly not require termination. The reason for this is, that these GPIOs have the `GPIORXDIS` bit set, which effectively disconnects the pad from the internal logic by disabling the input buffer. This bit - besides `GPIOTXDIS` - can also be set explicitly by using the gpio macro `PAD_NC(pad, NONE)`. In some cases, a pull resistor may be required due to bad board design or when a vendor sets the RX/TX disable bits together with a pull resistor and schematics are not available to check if the pad is really unconnected or just unused. In this case the pull resistor should be kept. Pads defaulting to native functions usually don't need special handling. However, when pads requiring external pull-ups are missing these due to bad board design, they should be configured with `PAD_NC` to disconnect them internally. Rewrite the documentation to reflect these new findings. Also clarify the comment in soc/intel gpio code accordingly. Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10Documentation/releases: Fill in coreboot 4.14 release notesPatrick Georgi
Change-Id: I79530c91424112247e485a5a41debc666e0072d4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10doc/relnotes/4.14: add Intel Xeon-SP support status changeJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changesKyösti Mälkki
Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-09Documentation/gerrit: Document our Gerrit user roles and proceduresPatrick Georgi
Document the roles we have on review.coreboot.org, the expectations associated with them, and how to become part of any of these groups. Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52265 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne additionFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/i2c/generic: Set S0W to D3hot for wake deviceTony Huang
If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-03util/sconfig: Add support for discontiguous FW_CONFIG fieldsTim Wawrzynczak
Sooner or later, some board was going to need extra FW_CONFIG bits for a field that was already in production, so this patch adds support for adding extra (unused) bits to a field. The extra are appended via a syntax like: `field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...` and the suffixed bits are all treated as if they are contiguous when defining option values. BUG=b:185190978 TEST=Modified volteer fw_config to the following: field AUDIO 8 10 | 29 29 | 31 31 option NONE 0 option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 option RT1011_ALC5682I_I2S 6 option AUDIO_FOO 7 option AUDIO_BAR 8 option AUDIO_QUUX 9 option AUDIO_BLAH1 10 option AUDIO_BLAH2 15 option AUDIO_BLAH3 16 option AUDIO_BLAH4 31 end which yielded (in static_fw_config.h): FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700 Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747 Reviewed-by: Duncan Laurie <duncan@iceblink.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29docs/mb/supermicro/x11ssm-f: rework flashing sectionMichael Niewöhner
The board can be flashed without adding a diode by just leaving VCC unconnected. Rework the flashing section to describes that. Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/asus/p5q: Document working fan control and FireWire portStefan Ott
Fan control and FireWire work fine on my board. Signed-off-by: Stefan Ott <stefan@ott.net> Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26mb/system76/oryp6: Add System76 Oryx Pro 6Tim Crawford
https://tech-docs.system76.com/models/oryp6/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe - M.2 SATA - MicroSD card slot - All USB ports - Integrated graphics using Intel GOP driver - Webcam - Ethernet - Internal microphone - Combined headphone + mic 3.5mm jack - Combined microphone + S/PDIF 3.5mm jack - Booting to Ubuntu Linux 20.10 and Windows 10 - Flashing with flashrom Not working: - S3 suspend/resume: System hangs on wake from S3 - Discrete/Hybrid graphics: Requires a new driver - Internal speakers: Enabled in separate patch Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16[RFC] Address the leftover TODO in soc/intel/cannonlakeFurquan Shaikh
Change-Id: I4c989de4d2af3e810fb0e4803d0fa2396917d93e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50829 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15Documentation: List the leadership meeting as one of our forumsPatrick Georgi
Change-Id: I00822cc631c5451862bd94683ff45289ecc75679 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-04-15sc7280: Provide initial SoC supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15Documentation/mb/ocp: Update Delta Lake documentationJonathan Zhang
Update OCP Delta Lake documentation following OSF (Open System Firmware) solution reaching DVT exit parity. This alternative host firmware solution uses FSP/coreboot/Linuxboot stack. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06Docs/mb/lenovo/t420: List working, tested and non-working featuresPiotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl> Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-03docs/mb/supermicro: add SUM tool for flashing with disabled MEMichael Niewöhner
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28mb/purism/librem_14: Move/fix touchpad interrupt GPIOMatt DeVillier
On production boards, the touchpad interrupt line was moved from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry, and update documentation to remove touchpad config issue. Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28documentation: Add documentation for Purism Librem 14Matt DeVillier
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26Documentation/coding_style: Issues not mentioned and cleanup patchesJulius Werner
This patch adds a bit of a "preamble" to the coding style to provide guideance on how it should be applied and how style questions that aren't mentioned should be handled. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24mb/system76/gaze15: Add System76 Gazelle 15Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not working: - Discrete/Hybrid graphics This requires a new driver to work correctly, which will be added and enabled later. Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22Documentation/coding_style: Add more details on include-orderingJulius Werner
This patch is trying to address some of the concerns raised in CB:50247 after the patch had landed. The preference for alphabetized headers was just supposed to discourage leaving headers completely unordered, and wasn't intended to disallow other intentional include orderings such as grouping local includes after system ones or specific ordering constraints that exist for technical reasons. This patch adds a few more sentences to try to clarify that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6825f4a57613fabb88a00ae46679b4774ef7110b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19doc/mb/lenovo/montevina: Update link within pageAngel Pons
Commit c4aa24fc121 (doc/mb/lenovo/montevina: Clarify use of bincfg) renamed a section, and the link referencing it by its old title no longer works. Update the link, and remove the `a completely new one` part from it as well, for consistency with the aforementioned commit. Change-Id: I22e8b3237dafb3397bc901804a57e905f806839d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-18Documentation/releases: Add note about CBFS stage format changePatrick Georgi
Change-Id: I2e4f1d1551141c6225e762631e52d71357112425 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-17Documentation: Describe the site-local hook in our config/build systemPatrick Georgi
Change-Id: Ia682b784540fa82e1f216f76d87d59a4f0b94486 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51546 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17Documentation: Add deprecation notice for SAR support in VPDFurquan Shaikh
This change updates the release notes for coreboot-4.14 to add deprecation notice for SAR support in VPD for Chrome OS platforms. BUG=b:173465272 Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-14doc/mb/lenovo/montevina: Fix constants for 16MiB flashNico Huber
The current values are actually for 32MiB and result in a brick if used with a 16MiB chip because of the invalid bios region. Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11Documentation/acpi: switch example from edge to level interruptsDmitry Torokhov
Configuring touch controllers to use edge-triggered interrupts is not recommended as it is very easy to lose an edge when kernel drivers disable the interrupt for one reason or another, and recovering from this condition requires workarounds in the kernel. Unfortunately the example setting up a touchpad used edge-triggered interrupts, and this set up has been propagating through the boards. Let's switch the example to use level interrupts instead. Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-07doc/mb/lenovo/montevina: Clarify use of bincfgNico Huber
`bincfg` is not creating anything new, it just converts from text to binary. Change-Id: I14e67ee8bc449d171a951f6edeaa9f9d0c04dbe1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51319 Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26mb/google/trogdor: Add new configs homestarxuxinxiong
New boards introduced to trogodor family. BUG=b:180668002 BRANCH=none TEST=make Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-24doc/mb/ocp: Update DeltaLake for VPD variables used in LinuxBootJohnny Lin
u-root commits: bmc_bootorder_override https://github.com/u-root/u-root/pull/1902 systemboot_log_level: https://github.com/u-root/u-root/pull/1922 Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-23Doc/releases/checklist.md: Clarify tag push commandAngel Pons
Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47813 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22Document Gigabyte GA-G41M-ES2LAlexey Vazhnov
To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l + configs/config.gigabyte_ga-g41m-es2l + lshw output examples + memory modules compatibility Tested in Devuan 4 Chimaera. Tested from exact steps from this documentation. Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2021-02-22Documentation: move `coding_style.md` inside contributing/Alexey Vazhnov
Keep less files in the root directory. Change-Id: I9eebd0b0826181340ead41af5284362d1cca09d7 Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-17treewide: Remove trailing whitespaceMartin Roth
Remove trailing whitespace in files that aren't typically checked. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8dfffbdeaadfa694fef0404719643803df601065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`Paul Menzel
It’s good practice to put the unit into the name. Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-09Doc/mb/lenovo/montevina_series: Use Makefile to generate IFDEvgeny Zinoviev
util/bincfg's Makefile already has target that generates flash descriptor. Use it instead. Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09Documentation: Use correct KiB/MiB units instead of KB/MBEvgeny Zinoviev
Fix a common mistake of using KB/MB where KiB/MiB is what actually is meant. 1 MB = (10^3)^2 = 1000000 1 MiB = (2^10)^2 = 1048576 Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39685 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06Documentation: Codify some guidelines for headers and chain-includingJulius Werner
There has been some repeated discussion about how header includes should be formatted, specifically on the topic of chain-including. The coding style currently doesn't say anything about the topic but clearly people have some basic assumptions. This patch tries to codify some common ground rules that are supposed to reflect the existing practice. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28Update util.md documentationMartin Roth
This is the new output of the util_readme.sh script. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25Documentation: Add documentation on jenkins buildersMartin Roth
Put this in a new directory called 'infrastructure' and make a link and an index.md file for the directory. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-24Doc/mb/lenovo/Sandy_Bridge_series.md: Clarify installationAngel Pons
Unlike Ivy Bridge series, there isn't a method to flash coreboot internally when running vendor firmware (yet). Until someone finds a way to bypass flash protections, the first flash has to be done externally. Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24Doc/mb/lenovo: Correct typoAngel Pons
Change-Id: If31c59f21c5533d8b5b015c9e60edd6e4e7072e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49847 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23soc/intel/apl: drop LPC pad configuration codeMichael Niewöhner
Drop LPC pad configuration code since all boards now do pad configuration on their own. The comment about LPC_CLKRUNB when using eSPI is moved to `Documentation/getting_started/gpio.md`. Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12Documentation: Fix toctree and remove dead linksPatrick Rudolph
Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12Documentation: Add known bugs of x86_64 code on real hardwarePatrick Rudolph
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled. The bugs are so strange that no root cause could be found yet. Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-24Documentation: Add Beaglebone Black documentationSam Lewis
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14Doc/mb/lenovo: Explain simpler GM45 flash method firstAngel Pons
Do not mislead newcomers into thinking the GM45 series laptops are hard to flash. Describe the simple coreboot flashing procedure first, then explain how to remove the ME firmware and use a custom flash layout. Also, reword a sentence on the simple flashing procedure for clarity. Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14Doc/mainboard: Sort Lenovo laptop generation groupsAngel Pons
GM45 is older than Arrandale, so swap their order. Change-Id: I5b94d940c0378dd561535257d3352700fd482527 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-11Docs/cbfstool: Add details about memory mapped window handlingFurquan Shaikh
This change adds details memory mapped window handling in cbfstool required for x86 platforms. It also captures the details about the newly added support for multiple decode windows. BUG=b:171534504 Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-05Documentation/mainboard/ocp: Update DeltaLakeJonathan Zhang
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has reached EVT exit parity. Update the documentation accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-27docs/mb/supermicro/x11-lga-series: Update documentationMichael Niewöhner
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726 - Add missing reference to X11SSH-F - Drop TODO reference; there are no TODOs left Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27{docs/,}mb/supermicro/x11ssh-tf: drop TODO sectionMichael Niewöhner
Drop the TODO comment, since there is no TODO left. Also drop the now obsolete TODO section from the board documentation. Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-27docs/mb/supermicro/x11ssm-f: Update board documentationMichael Niewöhner
- Drop vanished issue on PCIe warning - Drop TODO section, since the TODOs are done - Document the jumper J6, that was not documented by the vendor. Its function has been determined by dissecting a dead board. - The flash is not socketed anymore. Drop that note and compress the whole paragraph. Also add a note about flashing via the BMC web interface. Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-22Documentation: Mention newer Intel μ-code updates in 4.13 release notesPaul Menzel
Start a new section *Notes* for these kind of information. Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22Doc/releases/checklist.md: Fix up URLsAngel Pons
Use angle brackets so that they appear as links, and update a link to a Gerrit change to use the current format. Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22Doc/releases/checklist.md: Add reminder to unpack relnotesAngel Pons
Explicitly add this easy-to-forget step. Also add a missing period. Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/kontron: Add Kontron mAL10 COMe module supportMaxim Polyakov
This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20Documentation/releases: Update for 4.13Angel Pons
Fill in some blanks for 4.13, mark it done, add template for 4.14. Also update the list of vboot supported boards. Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20mb/clevo/kbl-u: Add Clevo N130WU/N131WUFelix Singer
Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-19doc/relnotes/4.13: Remove duplicated `CPU`Angel Pons
Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19doc/relnotes/4.13: Fix random spelling mistakesNico Huber
Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19Doc/relnotes/4.13: Add details about resource allocator v4Furquan Shaikh
This change adds details about the new resource allocator v4 in coreboot to the release notes for 4.13. Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19doc/relnotes/4.13: Add changes to log-level configurabilityNico Huber
Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19doc/relnotes/4.13: Add note about PCI bus mastering Kconfig optionsFelix Singer
Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13Doc/relnotes/4.13: Add several relevant changesAngel Pons
While some of these have little impact, they are worth mentioning here. Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-12Delete mainboard/google/chezaJulius Werner
Work on this mainboard was abandoned and never finished. It's not really usable in its current state, so let's get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-11Documentation/releases: Add ASan to 4.13 relnotesHarshit Sharma
Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-10mb/hp: Add HP EliteBook Folio 9480mIru Cai
The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09Documentation: Introduce HP Sure Start and the method to bypass itIru Cai
Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/purism/librem_cnl: Add new variant 'Librem Mini v2'Matt DeVillier
Add Kconfig entries, and update existing documentation to accomodate both v1/v2 versions of the board. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31docs/librem_mini: update CPU, known issues sectionMatt DeVillier
Both 8565U and 8665U CPUs are used in the Librem Mini. SATA issue updated based on addition of HSIO PHY tuning params and resulting changes. Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30.gitignore: Split into subdirectory filesPatrick Georgi
There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph
SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-20mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variantBill XIE
This adds another X11 series board, the X11SSH-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19Documentation: Fix spelling of *assumptions*Paul Menzel
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19drivers/intel/usb4: Add driver for USB4 retimer deviceDuncan Laurie
The USB4 retimer device needs to declare a _DSM with specific functions that allow for GPIO control to turn off the power when an external device is not connected. This driver allows the mainboard to provide the GPIO that is connected to the power control. BUG=b:156957424 Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30lenovo/t440p: Add HDA verbs from the OEM firmwareIru Cai
To get the HDA verbs from the OEM firmware, open the firmware with UEFITool, search for the existing HDA verbs, extract the UEFI module and look for the verbs. Copy the consecutive 4 dword sets that look like HDA verbs. It is tested to make audio output from both the speaker and headphone work. Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28doc/mb/ocp: update deltalake server documentationJonathan Zhang
Upon completion of 2nd build/test/release cycle of Deltalake server alternative firmware engineering, update the document. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28Documentation/mainboard: Add Missing OCP Delta Lake LinkChristian Walter
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-25Documentation/getting_started/kconfig.md: Add a note about Kconfig defaultsElyes HAOUAS
When the declaration is done after the default, menuconfig will see that symbol defined at the first place where kconfig tool will find it. For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we will see it defined at ""src/mainboard/51nb/Kconfig" which is odd. Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21Documentation: Add ASan documentationHarshit Sharma
Change-Id: I710ea495798597189941620c7e48fd5aa7476781 Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-11strongbad / coachz : Add Initial SupportBob Moragues
BUG=b:162409909 BUG=b:164196066 BRANCH=NONE TEST=Verify build of strongbad target Signed-off-by: Bob Moragues <moragues@chromium.org> Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10soc/amd/picasso: Move APCB generation out of picassoRob Barnes
Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31Documentation: Discuss how we use languagePatrick Georgi
Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>