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2020-03-09Documentation: Add Montevina ThinkPads common pageEvgeny Zinoviev
- Add a common page about Montevina ThinkPads. - Describe how to disable ME and remove its firmware on these models. - Describe vendor flash layouts. Thanks to swiftgeek for his help when writing this, especially the last paragraph and flash layouts. Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06nb/intel/haswell/peg: Add PEG driver stubChris Morgan
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded. Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-04util: Remove viatoolAngel Pons
It somehow creeps into `make clean`, but is not used at all. Since no VIA platform remains in coreboot, drop the utility as well. Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpioRajat Jain
Add new helper function in the acpigen library, that use the underlying soc routines. Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7 Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02Documentation: Add Heads to payloadsPatrick Rudolph
Add a small description about Heads. Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02Documentation: Add tutorial for me_cleaner on Lenovo devicesPatrick Rudolph
Add a tutorial how to use ME cleaner, and give some basic steps to strip the ME. Update the Lenovo Sandy Bridge documentation that no issues could be observed on X220 and give an example flash layout. Tested on Lenovo X220 with stripped ME and found no issues: commit: cbc5b99ac9e5856631109b1e7f20e80799beb1e4 * Displayport * VGA * USB * Bluetooth * Wifi * Wifi-kill switch * libgfxinit * SATA * Audio * SD-card * Ethernet * Keyboard * Fn-Keys * Display brightness * ACPI S3 resume * Battery events * CPU temperature reporting * FAN managment * Stress test stable * Youtube videos over Wifi * stress -c 2 -m 1 -d 1 * glxgears Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-28Docs/project_ideas.md: Add a memtest libpayload based payloadArthur Heymans
Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-24Documentation/project_ideas: Update after 2019Patrick Georgi
The coverity project is done, for the most part, so drop it. Expand a bit on the scope of the toolchain binary project, and point out that the Ghidra project already has code from GSoC 2019 but could be developed further. Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24Documentation: getting_started/gpio.md: fix markupIvan Labáth
Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d Signed-off-by: Ivan Labáth <iger@labo.rs> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39082 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19Documentation: soc/amd/psp: Use real table markupEvgeny Zinoviev
Currently, tables on this page are formatted as code blocks with ASCII tables. Make it real beautiful tables. Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19Documentation: Use inline code block for kernel parameterEvgeny Zinoviev
Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-18Documentation: Fix style issues on Lenovo X301 pageEvgeny Zinoviev
- Fix lists markup - Some minor fixes in the text (e.g. lowercases) Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17Documentation: mb/lenovo: Make X1 uppercaseEvgeny Zinoviev
x1 -> X1. Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17Documentation/lenovo: Replace RST code with markdownPatrick Rudolph
Latest Sphinx supports up path traversal in markdown. Replace old RST code that's no longer needed to prevent it being copy and pasted. Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17Documentation: Remove confusing xyz0 naming convention for Lenovo devicesPatrick Rudolph
Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge. Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s. Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17Documentation: ifdtool/layout: use real table for FD regionsEvgeny Zinoviev
Current doc transpiles to something completely unreadable. Change-Id: I197deb52974c88e067bc1615986a42c889214888 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17Documentation/superio: add formatting to generic PNP documentationFelix Held
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12doc/tutorial/part1.md: Add commands for yum- & pacman-based distroPatrik Tesarik
* Add additional information on non-debian cli tools * Improve spellings and descriptions to the best of my knowledge Adding info about needed tools in other distribution's package managers was requested at the coreboot beginner's workshop at 36C3. Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11Documentation/soc/amd/family17: Update to match current designMarshall Dawson
The Picasso no longer intends to implement a hybrid romstage, opting instead for a more traditional bootblock/romstage/ramstage. Update the documentation to reflect this. Clarify additional details that have come to light since the last revision. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11Documentation/soc/amd: Add PSP integration informationMarshall Dawson
Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-09Documentation: Remove qemu aarch64 from project ideasPatrick Rudolph
This has been implemented last year. Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09Documentation: Mark up register names as codePaul Menzel
Change-Id: I708385bca8edcd74b0d4c0a3ecc181b6ccd30c2b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38721 Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09Documentation: Indent code blocks instead of using ```Paul Menzel
Both versions are correct, but especially for one liners indenting them with four spaces instead of using ``` blocks helps readability of the source file. Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720 Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05Documentation: xx30 ThinkPads internal flashingEvgeny Zinoviev
Add detailed instructions on how to unlock protected SPI ranges and flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by exploiting stock BIOS security issues. Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-30Documentation/vendorcode/eltan: Update security documentWim Vervoorn
Update the security document to reflect the current state of the coreboot implementation. Add more detail and document the change to the public vboot API. BUG=N/A TEST=build Change-Id: I228d0faae0efde70039680a981fea9a436d2384f Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30Documentation/mainboard/facebook/monolith.md: Update to beta statusWim Vervoorn
Update to reflect the beta status of the code. BUG=N/A TEST=build Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-29Documentation/mainboard/facebook/monolith.md: Add flash componentsWim Vervoorn
Add description of the procedure to create the flash components for this system. BUG=N/A TEST=N/A Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-27Doc/mb/lenovo: Shrink picture for x301Bill XIE
Fix a non-standard larger picture not handled in time before merging. Change-Id: Ia494484cd0eff6b19408b065264911d0093ceeb0 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-01-27mainboard/system76: Add System76 Lemur Pro (lemp9)Jeremy Soller
The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support in coreboot is developed by System76 and provided as the default firmware option. Testing is done on a pre-production model expected to be identical from a firmware perspective to the production model. Working: - Payload - Tianocore - CPU - Intel i7-10510U - Intel i5-10210U - EC - ITE IT5570E running https://github.com/system76/ec - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys - Battery - Charger, using AC adapter or USB-C PD - Suspend/resume - Touchpad - GPU - Intel UHD Graphics 620 - GOP driver is recommended, VBT is provided - eDP 14-inch 1920x1080 LCD - HDMI video - USB-C DisplayPort video - Memory - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM - Networking - M.2 PCIe/CNVi WiFi/Bluetooth - Sound - Realtek ALC293D - Internal speaker - Internal microphone - Combined headphone/microphone 3.5-mm jack - HDMI audio - USB-C DisplayPort audio - Storage - M.2 PCIe/SATA SSD-1 - M.2 PCIe/SATA SSD-2 - RTS5227S MicroSD card reader - USB - 1280x720 CCD camera - USB 3.1 Gen 2 Type-C (left) - USB 3.1 Gen 2 Type-A (left) - USB 3.1 Gen 1 Type-A (right) Not working: - TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0 are not currently supported by the intel fast_spi driver. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-23Documentation: link asus p5q on mainboard pageFelix Held
Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-21mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)Ivan Vatlin
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2 Signed-off-by: Ivan Vatlin <jenrus@tuta.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-20Documentation/superio: add generic PNP device documentationFelix Held
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-18documentation: Add documentation on setting up mainboard GPIOsTim Wawrzynczak
The new documentation describes typical ways that mainboards will set up their GPIOs, as well as the distinction between "early" and "normal" GPIOs. It also describes the typical properties that GPIO configuration will cover. Change-Id: I279eec4ed2bb0248a2bdb363fb73b40b8272267f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-01-14Documentation: document non-Docker sphinx installation and usageFelix Held
Also update the known-good versions of the needed tools. Change-Id: I0f63860beb0a8a00360752318236e302c7170977 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10{Documentation,soc/intel}: Fix typoElyes HAOUAS
Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09acpi: Be more ACPI compliant when generating _UIDPatrick Rudolph
* Add function to generate unique _UID using CRC32 * Add function to write the _UID based on a device's ACPI path ACPI devices that have the same _HID must use different _UID. Linux doesn't care about _UID if it's not used. Windows 10 verifies the ACPI code on boot and BSODs if two devices with the same _HID share the same _UID. Fixes BSOD seen on Windows 10. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-26Doc/tutorial/part2.md: Align headings with part1.mdAngel Pons
Substitute `Part` with `Step` on this file's headings and use present tense instead of gerund. Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/tutorial/part1.md: Fix minor formatting issuesAngel Pons
Make sure all titles are capitalized, and add a missing period. Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26Doc/index.md: Fix a typoAngel Pons
Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-26Doc/releases/checklist.md: Correct some inconsistenciesAngel Pons
Use periods on every element of a list, and make `IRC` uppercase. Also, correct a grammar mistake that slipped through. Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-12-22superio/common: Add more ACPI methodsPatrick Rudolph
* Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-16Documentation: Extend release checklist (list to-be deprecated boards)Patrick Georgi
Make it part of the release process to note not only what config flags / code properties etc will be deprecated, but to also spell out which boards would be affected at the time of the release. Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD sectionAngel Pons
Change-Id: Ic94dd7381e9a107081011d083286d27005148557 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-12Documentation: Fix EC type for facebook and portwell boardsWim Vervoorn
Board description contained incorrect EC type. Change EC type to ITE8528 BUG=N/A TEST=build Change-Id: Ib5af79fb00bfdfc5dbe001b60010a74bddc696e2 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12Documentation: enable ditaa integrationPatrick Georgi
For prettier diagrams: http://ditaa.sourceforge.net/ Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-11Documentation: Fix table and layoutPatrick Georgi
The table wasn't pretty enough so sphinx complained, while the second paragraph had trailing whitespace, could be wrapped differently and also came with a typo. Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-10Documentation: Describe how to deal with snooping https proxiesPatrick Georgi
Disabling SSL verification is far from optimal, but depending on the circumstances may be the most practical way, so describe how to do that instead of leaving users confused. It's also not _that_ bad because git's hashing scheme should uncover most attempts to tamper with code, either when checking signed tags or when people push (and see lots of modified commits). State the command in a way that isn't conductive to careless copy & paste. Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-09Documentation: Move ACPI documentation in a subindexArthur Heymans
Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09Documentation: Remove redundant 'documentation'Arthur Heymans
We are already in documentation so it should be obvious that other links point to other documentation. Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06mb/facebook/monolith: Add Facebook MonolithWim Vervoorn
The board is booting Linux and has been briefly tested. SeaBIOS, TianoCore payload and Linux as payload all seem to work fine. BUG=N/A TEST=tested on Facebook Monolith Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-29Documentation/4.12-relnotes.md: Add SMMSTORE as production readyArthur Heymans
Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29Documentation: Add SMMSTORE documentationArthur Heymans
This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-28Documentation: Rework staging and commit informationDavid Hendricks
This patch does two things: - The CLI and Git Cola sections contained some duplicated information about pushing patches, which is now factored out into its own section. - The draft workflow is now disabled, so that part has been reworded to describe how to submit a private patch. Signed-off-by: David Hendricks <david.hendricks@gmail.com> Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22Documentation/releases: Update checklistPatrick Georgi
Having the release notes mostly ready one week before the release allows for better review. Some statistics, the actual release date and commit ID can only be filled in on release day, but there's a tried & true technique for that: placeholders. It's also a nice touch to have the release notes of a release within its source tarballs, so push them right before creating the release (since changes in Documentation/releases won't break coreboot in any way). Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: Drop reference to piratenpadPatrick Georgi
Piratenpad is dead. Change-Id: Id9cfb68f6c6e05d1af2a526c817713a92220d370 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36958 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: Releasing includes announcing on the listPatrick Georgi
Change-Id: I063997d51a80b1b244a0cb35ae90446610ef2c21 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36975 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Documentation/releases: 4.11 isn't "upcoming" anymore.Patrick Georgi
Change-Id: I7102519b171c3e5269fefaa66d12d605f5d9ddb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36974 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove MIPS architectureJulius Werner
The MIPS architecture port has been added 5+ years ago in order to support a Chrome OS project that ended up going nowhere. No other board has used it since and nobody is still willing or has the expertise and hardware to maintain it. We have decided that it has become too much of a mainenance burden and the chance of anyone ever reviving it seems too slim at this point. This patch eliminates all MIPS code and MIPS-specific hacks. Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20Remove imgtec/pistachio SoCJulius Werner
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation/releases: Finalize 4.11, start 4.12Patrick Georgi
Fill in some stats using our repo analysis scripts in util/release/, thank the contributors, add some prose about notable achievements since 4.10. Also start a new doc for 4.12. Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation: Remove duplicated entryPatrick Rudolph
The mainboard was accidently added due to bad rebase. Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19Documentation: Reword Supermicro X10SLM+-F datasheet referencesPaul Menzel
Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19docs: intel fsp: add memory retraining bug on SPS systemsMichael Niewöhner
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18Documentation/releases: Add libgfxinit changes in 4.11Nico Huber
Change-Id: Id7babdc9b1d908fa90ebac098a019615fa00b973 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18Documentation/releases: Add more c-env-bb platforms for 4.11Nico Huber
Change-Id: Ie5c83befc8e595016c63729a19e7e71438c996b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-15Documentation/mb/facebook/fbg1701.md: Update microcode blobFrans Hendriks
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15Documentation/mb/portwell/pq7-m107.md: Update microcode blobWim Vervoorn
The microcode is available in 3rdparty microcode now. This ucode can be used. BUG=N/A TEST=build Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12Documentation: Add more entries to 4.11 release notesPatrick Georgi
Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11Documentation: Add some significant 4.11 release notesKyösti Mälkki
Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-11Documentation: Add some significant 4.11 release notesPatrick Rudolph
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-10arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans
Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07lib/cbfs: Add fallback to RO region to cbfs_boot_locateWim Vervoorn
With this change cbfs_boot_locate will check the RO (COREBOOT) region if a file can not be found in the active RW region. By doing so it is not required to duplicate static files that are not intended to be updated to the RW regions. The coreboot image can still be updated by adding the file to the RW region. This change is intended to support VBOOT on systems with a small flash device. BUG=N/A TEST=tested on facebook fbg1701 Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04Documentation: Add some significant 4.11 release notesKyösti Mälkki
Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2019-11-01Documentation: Fix typoPatrick Rudolph
The document isn't included in any toc-tree due to a typo. Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36540 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01mb/portwell/m107: Add Kingston memory supportWim Vervoorn
Add support for board revision 1.3 containing Kingston memory. BUG=N/A TEST=tested on portwell m107 module Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-30Documentation: Add amd_blobs license agreement textMarshall Dawson
AMD has generated a simpler and more flexible license agreement for using proprietary precompiled binary images. The new agreement is intended to cover all blobs in the directory structure below where the license resides and eliminates any unique agreements previously provided for individual products. Add a description of the repo, as well as the license agreement it contains. Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-29Documentation/releases: Note pending AMD fam12h removalJoe Moore
Change-Id: I386572c772ea9de571bbb9d51ef9090e9c429b99 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27Documentation/writing_documentation.md: Explain how to use dockerArthur Heymans
Using docker to build to documentation eases the process of building the documentation. Given that some versions of sphinx are incompatible, the option to use docker is presented first. Change-Id: I6c18f81a829364ada1859c04ba2dc4f886934bcc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36105 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft
- This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-24Documentation: trivial typo fix strcut/structMarty E. Plummer
Change-Id: I5e7d8e8a95e5bef23307eb50456a89e0e23c445a Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-23Documentation: Add a technote sectionArthur Heymans
Change-Id: I8676f89399a0def3409f19dc92e4f65924d0ba22 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23technotes/coreboot-image-generation: Fix markdownArthur Heymans
The manifest example has to be marked as code. The Manifest parsing section header should be L2 and finally # is a special character in markdown. Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23mb/supermicro/x11-lga1151-series: add x11ssm-f boardMichael Niewöhner
This adds another x11 series board, the X11SSM-F, which is similiar to X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and Ethernet interfaces. Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner
2019-10-22Documentation: Fix typoPatrick Georgi
Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-21Documentation: Add proposal for a comprehensive image assembly stagePatrick Georgi
I originally put up this document for discussion in 2015 (mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX4V2OSXAQC4B2VUENSFZEWRPPOVRH2/) (doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeIc7Vo/edit) It may be time to revisit the way we define our image layouts now that there are new fmap schemes for new vboot uses. The approach outlined in this document may or may not be the right one, but it's something we have, so let's discuss. Compared to the doc, this will * be updated (things changed in the last 3.5 yearws) * integrate feedback to the doc and on the mailing list back then Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21Documentation: Make sure ifdtool/index gets added to toctreeArthur Heymans
Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21Documentation/writing_documentation.md: Fix typoArthur Heymans
Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21sc7180: Provide initial SoC supportT Michael Turney
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-20mb/lenovo/x200: Add ThinkPad X301 as a variantBill XIE
It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16mainboard/ocp/monolake: Hide IIO root ports before memory initAndrey Petrov
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-16Documentation/mainboard/facebook: Add rev 1.3Wim Vervoorn
Add rev 1.3 of the fbg1701 board. This adds Kingston memory. BUG=none TEST=none Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-15soc/intel/common/block/sgx: Fix crash in MP initPatrick Rudolph
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written when already locked by the sibling thread. In addition it loads microcode updates on all threads. To prevent such race conditions only call the code on one thread, such that the MSRs are only written once per core and the microcode is only loaded once for each core. Also add comments that describe the scope of the MSR that is being written to and mention the Intel documents used for reference. Fixes crash in SGX MP init. Tested on Supermicro X11SSH-TF. Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15mainboard/lenovo/t410: Add new portNicolas Reinecke
The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-14Documentation/gfx: Update support list of libgfxinitNico Huber
Also get rid of some manual hyphenation. Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-07src: Capitalize Super I/OElyes HAOUAS
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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