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Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.
Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49
Tested on:
* CFL platform with IGD
* CFL platform without IGD
Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.
Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.
TEST=the patch was ran on affected HW and success was reported
Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As Intel doesn't even document known bugs add a list of
FSP bugs here.
Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch moves mp service ppi document from icelake/MultiProcesorInit.md
to ppi/mp_service_ppi.c.
Change-Id: I1bbaeb2644f219b5a1fda0c7c4b594184d53958c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31840
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some new feature added into FSP specification to perform dispatching
of external PPI service from boot firmware (coreboot) to FSP.
Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch combines open source documentation for Intel FSP
specification.
Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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