coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-18	soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs	Raul E Rangel
	BUG=b:147042464 TEST=Boot trembyle to OS Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19	Documentation: soc/amd/psp: Use real table markup	Evgeny Zinoviev
	Currently, tables on this page are formatted as code blocks with ASCII tables. Make it real beautiful tables. Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-11	Documentation/soc/amd/family17: Update to match current design	Marshall Dawson
	The Picasso no longer intends to implement a hybrid romstage, opting instead for a more traditional bootblock/romstage/ramstage. Update the documentation to reflect this. Clarify additional details that have come to light since the last revision. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11	Documentation/soc/amd: Add PSP integration information	Marshall Dawson
	Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-30	Documentation: Add amd_blobs license agreement text	Marshall Dawson
	AMD has generated a simpler and more flexible license agreement for using proprietary precompiled binary images. The new agreement is intended to cover all blobs in the directory structure below where the license resides and eliminates any unique agreements previously provided for individual products. Add a description of the repo, as well as the license agreement it contains. Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-01	Documentation/soc/amd: Add Family 15h	Richard Spiegel
	Create documentation for AMD Family 15h. BUG=none. TEST=none. Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-13	Documentation/soc/amd: Add Family 17h	Marshall Dawson
	Begin a directory for AMD soc devices and add an explanation of how Family 17h works. Newer AMD systems use a unique paradign for initializing the x86 processors. Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>