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2019-04-23hifive-unleashed: update documentation to match current statePhilipp Hug
Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-11Documentation: Make lenovo codenames human readablePatrick Rudolph
Use rst parser to convert the csv to markdown tables. Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-10Doc/mb/asrock/h110m: update info about PEGMaxim Polyakov
- Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported. Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06Doc/mb/asrock/h110m: Fix the linksMaxim Polyakov
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-19mainboard: Add ASRock H110M-DVSMaxim Polyakov
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard. Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio. TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation. Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload. Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-14Documentation: Add Asus F2A85-MBalazs Vinarz
Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-26mb/qemu-riscv: update to match current qemu versionPhilipp Hug
Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17mb/lenovo/x220: Add x1 as a variantBill XIE
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09Doc/mb/asrock/h81m-hds: Link to the Haswell documentationTristan Corrick
Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-09Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixedTristan Corrick
The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Also add a link to the known issues for Haswell, which has some information on PCIe. Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixedTristan Corrick
PCIe graphics for display output still doesn't work, but that is now listed in the Haswell-specific documentation. Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03Doc/nb/intel/haswell: Add a list of known issuesTristan Corrick
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30455 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-29mainboard: Add Supermicro X10SLM+-FTristan Corrick
This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-24Documentation/nb/intel: Add Haswell documentationTristan Corrick
At the moment, this just gives some details on the MRC. Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-20Documentation/mb/intel/kblrvp11: Fix table formattingJonathan Neuschäfer
Without this patch, Sphinx 1.7.9 prints the following warning, and doesn't emit the table as HTML: /.../Documentation/mainboard/intel/kblrvp11.md:1: WARNING: Malformed table. +------------------+---------------------------------------------------+ | CPU | Kaby lake H (i7-7820EQ) | +------------------+---------------------------------------------------+ | PCH | Skylake PCH-H (called SPT-H) | +------------------+---------------------------------------------------+ | Coprocessor | Intel ME | +------------------+---------------------------------------------------+ Change-Id: I17920398126d57eb8815c45e4a0d4b100f46004a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19Documentation/mainboard/lenovo/t420.md: fix typoMichael Bacarella
Picture of mainboard wasn't displaying. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: Ia70f5d5ad2fdf4c0e811ab92a817375a89694122 Reviewed-on: https://review.coreboot.org/c/30170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19Documentation/../../kblrvp11: Add RVP11 documentationPraveen hodagatta pranesh
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd Reviewed-on: https://review.coreboot.org/c/29859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
2018-12-19Documentation/soc/intel/icelake: Fix references between documentsJonathan Neuschäfer
Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-07mainboard/lenovo/t430s: Add ThinkPad T431s as a variantBill XIE
The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - C-based native graphic init (since T431s has eDP instead of LVDS) - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/30021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-05Documentation/mainboard/lenovo/t420.md: add pic of chipMichael Bacarella
Provide pic of the flash IC with pinouts labeled, as well as additional text about the chip. Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Change-Id: I9046fa63dcd4d192836417efac68ca7587ac1c91 Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com> Reviewed-on: https://review.coreboot.org/c/30027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-27Documentation/../../dragonegg: Add dragonegg coreboot development documentationSubrata Banik
Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27Documentation/../../icelake_rvp: Add RVP coreboot development documentationSubrata Banik
Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-19Documentation: Add W530 / T530Patrick Rudolph
Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-17mb/intel/dg43gt: Add documentationArthur Heymans
Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-16mainboard: Add ASRock H81M-HDSTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-10mb/lenovo/t400: Improve docking codePatrick Rudolph
* Remove dead code * Add support for types 2504 and 2505 * Print dock info at romstage entry * Improve dock disconnect for type 2505 * Move defines into dock.h for future ACPI code * Reduce timeouts according to spec to decrease boot time on error * Fix no docking detection (reduces boot time by 1 second) * Configure GPIO LDN before reading GPIOs * Use Kconfig values instead of fixed defines * Add documentation Tested on Lenovo T500 with docking 2504 and 2505. Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-29Documentation/mainboard: Add emulation/spike-riscv.mdJonathan Neuschäfer
Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-08Documentation: Improve elgon documentationPatrick Rudolph
* Convert PNG to JPG and reduce image quality. * Mark flash IC and USB serial connector. * Mark SPI programming header. * Add programming header pinout. Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-06Documentation/mb/sifive: Fix dead linksJonathan Neuschäfer
SiFive's website was reorganized, which broke our links to PDF files. Update these links to the current ones, obtained by browsing https://sifive.com/documentation/. Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-05Documentation/mainboard/gigabyte/ga-h61m-s2pv: Expand pageAngel Pons
Uniformize the Yes/No in the tables, expand the internal programming section and explain how to patch a defective flash descriptor. Change-Id: I972bb8948c29ce0eba46daa92ce6b6052db7b063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04Documentation: Spell "blob" in lowercaseJonathan Neuschäfer
It's not an acronym (outside of database software). Change-Id: I529561e4fc9889be7f9d6bd6d5f9a876e2007671 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03Documentation/mb/lenovo/t4xx_series: Change "Steps to access the flash IC" ↵Jonathan Neuschäfer
to sub-heading This heading should not be a top-level heading, because it's not at the top of the file. Also remove the trailing colon, because it's unnecessary in a heading. Change-Id: I0685bb8734ad899c29618d24c0497e4fb8c0d01c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-30Documentation: Add basic flashing tutorial for LenovoPatrick Rudolph
* Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30mainboard/opencellular/elgon: Add mainboard supportPhilipp Deppenwiese
Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-14riscv: add trampoline in MBR block to support boot mode 1Philipp Hug
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10soc/sifive/fu540: Add driver for OTP memoryPhilipp Hug
Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-08-23mb/foxconn/d41s: Add mainboardArthur Heymans
This supports the Foxconn d41s, d42s, d51s, d52s. The following is tested (SeaBIOS 1.12 + Linux 4.9) and works: - COM1 - S3 resume (with SeaBIOS needs sercon disabled) - Native graphic init on VGA output - SATA - USB - Ethernet - PS2 keyboard The base for this mainboard port was the Intel D510MO port. Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28227 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03mainboard: Add ASUS P8H61-M LXTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This code is based on the output of autoport. The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 4601). This board works well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. To summarise: the only known issues are that S3 suspend/resume doesn't work, and that there is no automatic fan control via the super I/O. Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-17Documentation/mb/sifive: Update TODO list; UART driver has been mergedJonathan Neuschäfer
See 894e3a9ec8 ("drivers/uart: Add a driver for SiFive's UART"). Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/27398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-28Documentation: Add Gigabyte to list of mainboardsAngel Pons
Gigabyte was not in the list of vendors in the mainboard-specific documentation. This made a newly added mainboard page difficult to locate. This commit adds Gigabyte and links said mainboard in the mainboard-specific documentation main page. Change-Id: I8839e1c1176fbdc3dd9da616f68c58e8e1cf1b16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-19Documentation: Add cavium SoC and mainboardPatrick Rudolph
* Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-12Documentation: Add Gigabyte GA-H61M-S2PVAngel Pons
Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/26964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-30Documentation: Update index.md and move filesPhilipp Deppenwiese
* Add more subdirectories and index.mds. * Move "getting started" and "lessons" into sub-directories. * Move "NativeRaminit" into northbridge/intel/sandybridge folder. * Move "MultiProcessorInit" into soc/intel/icelake folder. * Reference new files Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26262 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28Documentation: Add HP Compaq 8200 and NPCD378Patrick Rudolph
Change-Id: I56db0cc11cfa5a1a537091553393542312d4f212 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26543 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19Documentation: Add mainboard section to indexJonathan Neuschäfer
Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/26266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08Documentation: Add HiFive Unleashed documentationJonathan Neuschäfer
Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 18:56:45 +0000