coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-08-06	Documentation: Advertise support for OpenSBI	Patrick Rudolph
	Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-04-23	hifive-unleashed: update documentation to match current state	Philipp Hug
	Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-06	Documentation/mb/sifive: Fix dead links	Jonathan Neuschäfer
	SiFive's website was reorganized, which broke our links to PDF files. Update these links to the current ones, obtained by browsing https://sifive.com/documentation/. Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14	riscv: add trampoline in MBR block to support boot mode 1	Philipp Hug
	Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
	Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-17	Documentation/mb/sifive: Update TODO list; UART driver has been merged	Jonathan Neuschäfer
	See 894e3a9ec8 ("drivers/uart: Add a driver for SiFive's UART"). Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/27398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-08	Documentation: Add HiFive Unleashed documentation	Jonathan Neuschäfer
	Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>