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2019-11-10arch/riscv: Pass cbmem_top to ramstage via calling argumentArthur Heymans
Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-06Documentation: Advertise support for OpenSBIPatrick Rudolph
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-06-21Documentatioan: update stage handoff protocolXiang Wang
Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-10-30Documentation/riscv: Improve `index.md`Paul Menzel
1. Add dot/period to the end of sentences 2. Remove blank line at the end of the file 3. Break lines after 75 characters 4. Use RISC-V spelling 5. Add comma for clarity Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28654 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15riscv: add documentation for stages and payloadsRonald G. Minnich
Change-Id: Iff522e309e9cf9a31c1c79c24047d83d7fd0b00a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>