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2018-04-17Documentation/Intel: Adjust heading levelsJonathan Neuschäfer
Adjust the headings so that there is only one h1 tag per file. Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-08soc/intel/quark: Pass in the memory initialization parametersLee Leahy
Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12Documentation/Intel/Board: Update the Galileo checklistLee Leahy
Update the Galileo board implementation checklist. TEST=Build and run on Galileo Gen2 Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15137 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02Documentation/Intel/Board: Add Galileo checklistLee Leahy
Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Documentation/Intel/Board: Add analog switch linkLee Leahy
Add link for TI TS5A23159 specification. TEST=None Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15003 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-11lib: remove FLASHMAP_OFFSET config variableAaron Durbin
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define. Those 2 values are not consistent. Therefore, remove the Kconfig variable and defer to the #define generated by fmdtool. Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14765 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-21Documentation/Intel: Add more Galileo Gen2 linksLee Leahy
Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07Documentation/Intel: Making a bootable SD cardLee Leahy
Add a link to "Making a bootable SD card" TEST=None Change-Id: I5682fdd51a4ba37f97ad35475e11d9843f1498fb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-24Documentation/Intel: Add minimal APCI and TempRamExit documentationLee Leahy
Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19Documentation: x86 device tree processing and memory mapLee Leahy
Add documentation on: * FSP Silicon Init * How to start the x86 device tree processing for ramstage * Disabling the PCI devices * Generic PCI device drivers * Memory map support TEST=None Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13718 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: x86 add sleep state and minimal memory setupLee Leahy
Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: x86 Enable Serial OutputLee Leahy
Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13444 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: Add Galileo Gen 1 DocumentationLee Leahy
TEST=None Change-Id: Ic5a732dc27e772c4708a090ecd0c0af17dc5b056 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13606 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05Documentation: Fix links to Intel/documentation.htmlLee Leahy
Fix links to the documenation.html page which was renamed from x86Documenation.html. TEST=Verified documentation links and searched for x86Documenation.html Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02Documenation: x86 Quark/Galileo remove i586 warningLee Leahy
Leverage patch 13552 by adding USE_MARCH_586 to soc/intel/quark/Kconfig. TEST=None Change-Id: Ifac947db53e967b98b9494db3f6c3f8ee039ac73 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13561 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-02Documentation: Add x86 documentation for required filesLee Leahy
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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