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2024-01-05cpu/x86/64bit/mode_switch2: The reverse function to mode_switchPatrick Rudolph
Add another mode_switch assembly function to call x86_64 code from x86_32 code. This is particullary useful for BLOBs like mrc.bin or FSP that calls back into coreboot. The user must first wrap all functions that are to be called from x86_32 using the macro prot2lm_wrapper. Instead of using the original function the wrapped functions must be passed to the x86_32 BLOBs. The assembly code assume that 0-3 32bit arguments are passed to the wrapped function. Tested: - Called x86_64 code from x86_32 code in qemu. - Booted Lenovo X220 using x86_32 MRC using x86_64 console. Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-05vendorcode/google/chromeos: Use unsigned int for "factory_config"Subrata Banik
This patch ensures `chromeos_get_factory_config()` returns an unsigned integer value because factory config represents bit-fields to determine the Chromebook Plus branding. Additionally, introduced safety measures to catch future "factory_config" bit-field exhaustion. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79769 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-01-05util/ifdtool: Add support for disabling GPR0Reka Norman
On ChromeOS devices with updateable CSE firmware, the GPR0 (Global Protected Range) register is used to ensure the CSE RO is write protected even when the FLMSTR-based protection is temporarily disabled by coreboot to allow updating the CSE RW. For more details see Documentation/soc/intel/cse_fw_update/cse_fw_update.md Therefore to allow modifying the CSE firmware from the CPU, the descriptor must have both the FLMSTR-based protection disabled (which can be done using ifdtool --unlock), and GPR0 disabled. Add an ifdtool option for disabling GPR0. For now I've added support for all platforms for which I have the SPI programming guide. Support for more platforms can be added in the future if needed. BUG=b:270275115 TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked craask image, check the GPR0 field is set to 0. Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04vboot: Add firmware PCR supportYi Chou
To verify the boot chain, we will need to extend the PCR with the firmware version. And the server will be able to attest the firmware version of devices. The "firmware version" here is the RW firmware anti-rollback version, determined by the ChromeOS's signing infra, and will be verified in vb2api_fw_phase3, by comparing it with the version stored in the TPM. This version will be increased when there is critical vulnerability in the RW firmware. According to [1], PCRs 8-15 usage is defined by Static OS. Therefore PCR_FW_VER is chosen to be within that range. Ideally the existing PCR_BOOT_MODE and PCR_HWID should also be allocated in the same range, but unfortunately it's too late to fix them. Because PCRs 11 and 13 have been used for other purposes in ChromeOS, here PCR_FW_VER is set to 10. [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_05_3feb20.pdf BUG=b:248610274 TEST=Boot the device, and check the PCR 10 BRANCH=none Signed-off-by: Yi Chou <yich@google.com> Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79437 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04Documentation: Update internal URL'sJon Murphy
Update URL's to point to head rather than the deprecated refs/heads/master. Change-Id: I16f0c087762ff049115b67de3ac0b881aa4e4b40 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-04driver/wifi: DDR RFIM _DSM method function 3 report incorrect valueSimon Yang
The DDR RFIM _DSM method function 3 need to return: - 0: Enable DDR RFIM feature. - 1: Disable DDR RFIM feature. BUG=b:302084312 TEST=Build, dump SSDT to check _DSM function 3 return value Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
2024-01-04nb/intel/sandybridge/raminit: Honor SPD's dll_off_modePatrick Rudolph
In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.aslFelix Held
To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-03mb/intel/mtlrvp: add 512KB SI_EC FMAP regionDeepti Deshatty
This patch introduces the 512KB SI_EC FMAP region for storing the EC firmware, a necessary addition to support EC chips without internal flash memory. As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction with the Microchip EC1723, and the changes are verified. Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 BUG=b:289783489 TEST=build "emerge-rex coreboot chromeos-bootimage" is successful. changes are verified. EC Log: 23-11-06 17:46:49.564 --- UART initialized after reboot --- 23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3, os:f660f7,cmsis:42cf18,picolibc:6669e4] 23-11-06 17:46:54.609 D: Power state: S5 --> S5S4 23-11-06 17:46:54.620 D: Power state: S5S4 --> S4 23-11-06 17:46:54.620 D: Power state: S4 --> S4S3 23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087 23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0 Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79209 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03mb/google/rex/var/screebo: Prevent camera LED blinking during bootJason Chen
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot, preventing privacy LED blink. BUG=b:317434358 TEST=none Change-Id: I43044e64c2c3a645ec0cad2ac903cc19ac89c9af Signed-off-by: Jason Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79803 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-01-03cpu/x86/64bit/mode_switch: Simplify assembly codePatrick Rudolph
Drop the first argument specifying the number of arguments pushed to the stack. Instead always push the 3 arguments to stack and use the first one as function pointer to call while in protected mode. While on it add more comments and simplify register restore code. Tested: - On qemu can call x86_32 function and pass argument and return value. - Booted Lenovo X220 in x86_64 mode using x86_32 MRC. Change-Id: I30809453a1800ba3c0df60acd7eca778841c520f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79752 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64Patrick Rudolph
- Remove pointers in argument list passed to MRC to make sure the struct has the same size on x86_64 as on x86_32. - Add assembly wrapper to call the MRC with argument in EAX. - Wrap calling MRC in protected_mode_call_2arg, which is a stub on x86_32 Tested: Boots on Lenovo X220 using MRC in x86_32 and x86_64 mode. Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-02mb/google/fizz: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/razer: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting binary remains the same. Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/intel/kblrvp: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verificationJeremy Compostella
Enabling SSE2 accelerated RSA signature verification saves 4.7 ms of boot time. | modpow() function call | original | SSE2 Algorithm 2 | |----------------------------+----------+------------------| | coreboot/verstage - step 1 | 6.644 | 3.042 | | coreboot/verstage - step 2 | 1.891 | 0.757 | |----------------------------+----------+------------------| | Total (ms) | 8.535 | 3.799 | BUG=b:312709384 TEST=modular exponentiation is more than twice faster on rex0 Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79291 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-02mb/google/rex/var/karis: Enhance CNVi and PCIe switchingTyler Wang
1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI". 2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE". 3. Remove "ALC5650_NO_AMP_I2S" case in fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI" case. BUG=b:312099281 TEST=Build and test on karis Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79765 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31libpayload: Remove shell for loops in install Makefile targetPatrick Georgi
They always require special care so that line breaks and variable names are escaped properly. One loop can be removed entirely because install accepts multiple files to install in a target directories, the other loops were filled by find which can just call the commands on its own. Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79523 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31mb/google/nissa/var/craask: Add ILTK touchscreenRen Kuo
Add touchscreen ILTK for craaskwell. Refer to ILI2901A-A200 Data Sheet_V1.1_20231026. BUG=b:308873706 TEST=build and check touchscreen function on craask Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-12-31mb/google/dedede: Create dita variantSheng-Liang Pan
Create the dita variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:317292413 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DITA Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-31vendorcode/google/chromeos: Add API for Chromebook Plus checkSubrata Banik
This patch implements an API which relies on the chromeos_get_factory_config() function to retrieve the factory config value. This information is useful to determine whether a ChromeOS device is branded as a Chromebook Plus based on specific bit flags: - Bit 4 (0x10): Indicates whether the device chassis has the "chromebook-plus" branding. - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus hardware specifications. BUG=b:317880956 TEST=Able to verify that google/screebo is branded as Chromebook Plus. Change-Id: Iebaed1c60e34af4cc36316f1f87a89df778b0857 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-31vendorcode/google/chromeos: Add API to read factory configSubrata Banik
This code leverages the TPM vendor-specific function tlcl_cr50_get_factory_config() to fetch the device's factory configuration. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-31security/tpm: Retrieve factory configuration for device w/ Google TPMSubrata Banik
This patch enables retrieval of factory configuration data from Google TPM devices (both Cr50 and Ti50). This patch utilizes vendor-specific command TPM2_CR50_SUB_CMD_GET_FACTORY_CONFIG (68). The factory config space is a 64-bit, one-time programmable. For the unprovisioned one, the read will be 0x0. BUG=b:317880956 TEST=Able to retrieve the factory config from google/screebo. Change-Id: Ifd0e850770152a03aa46d7f8bbb76f7520a59081 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79736 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-29util/liveiso: Update to 23.11 releaseFelix Singer
The package 'bluezFull' got superseded by 'bluez'. So just remove the related line since 'bluez' is the default. Change-Id: Ibf72c37205017b27012064b311a9510136351c0f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-29util/docker/fedora: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-28mb/google/nissa/var/anraggar: add hook for WiFi SAR tablecengjianeng
As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-28mb/pcengines/apu2/mainboard: add/fix comments on PIRQ tableFelix Held
Align the comments on the PIRQ table entries for the PCI bridge devices to the external PCIe ports with the devicetrees of the different APU boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entriesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If08f7674509c953cf46c4e0d280edc9f863ef2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79675 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-28mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5Krystian Hebel
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28Documentation: Add Protectli to ships-with-coreboot hw listFilip Lewiński
Change-Id: Iff642f5122e7132d96177f2ed1680ece42aac095 Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-12-28libpayload: Add VBOOT_X86_RSA_ACCELERATION configJeremy Compostella
Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2 instruction set implementation of modulus exponentiation which is part of the RSA signature verification process. This option is enabled on CHROMEOS. | modpow() function call | original on rex0 | SSE2 on rex0 | |------------------------+------------------+--------------| | depthcharge - step 1 | 0.547 | 0.288 | | depthcharge - step 2 | 0.152 | 0.081 | | depthcharge - step 3 | 0.164 | 0.079 | |------------------------+------------------+--------------| | Total (ms) | 0.863 | 0.448 | | modpow() function call | original on brya0 | SSE2 on rex0 | |------------------------+-------------------+--------------| | depthcharge - step 1 | 0.693 | 0.248 | | depthcharge - step 2 | 0.172 | 0.065 | | depthcharge - step 3 | 0.223 | 0.067 | |------------------------+-------------------+--------------| | Total (ms) | 1.088 | 0.38 | BUG=b:312709384 TEST=modular exponentiation is about twice faster on rex0 and brya0 Change-Id: I801ebd7839261c6bd07fb218e1e36a7108e219bf Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-12-28mb/google/brox: Add new GFX devicesShelley Chen
Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2 ports). Copied the PLD placements from USB PLDs. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-27vboot: add VBOOT_X86_RSA_ACCELERATION configJeremy Compostella
Add `VBOOT_X86_RSA_ACCELERATION' Kconfig option to enable SSE2 instruction set implementation of modulus exponentiation which is part of the RSA signature verification process. BUG=b:312709384 TEST=Able to use SSE2 accelerated implementation on rex0 Change-Id: Ib6e39eb9f592f36ad3dca76c8eaf2fe334704265 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79289 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-27arch/x86/car.ld: Use VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE constantJeremy Compostella
Use the `VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE' constant defined by the vboot project instead of hard-coding the buffer size. Change-Id: I6039fc7cf2439535ca88663806bdcf99ad5089b0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-26drivers/intel/gma: Only show the choice when a VBT is to be addedArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-26Update vboot submodule to upstream mainJulius Werner
Updating from commit id c0cb4bfa: 2023-12-08 signer: sign_android_image.sh should die when image repacking fails to commit id 7c3b60bb: 2023-10-13 firmware/2lib: Use SSE2 to speed-up Montgomery multiplication This brings in 3 new commits: 7c3b60bb firmware/2lib: Use SSE2 to speed-up Montgomery multiplication 8bb2f369 firmware: 2load_kernel: Set data_key allow_hwcrypto flag 2b183b58 vboot_reference: open drive rdonly when getting details 6ee22049 sign_official_build: switch from dgst to pkeyutl da69cf46 Makefile: Add support for make 4.3 Also update the implementations of the vb2ex_hwcrypto_modexp() callback to match the API changes made in vboot. Change-Id: Ia6e535f4e49045e24ab005ccd7dcbbcf250f96ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-26drivers/intel/fsp2_0: Add boot mode stringsMarx Wang
The FSP boot mode showing in serial log is a magic number. In order to let user understand its meaning directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [SPEW ] bootmode is set to: 2 with this change: [SPEW ] bootmode is set to: 2 (boot assuming no config change) Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-26mb/google/myst: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26mb/google/skyrim: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-26soc/amd/stoneyridge/BiosCallOuts: add missing curly bracesFelix Held
When an if block has curly braces, the corresponding else block should also have curly braces. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1979873142469b1482097f9b4db487541a1b7a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-26soc/amd/common/pi/agesawrapper: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for all SoCs that include this code in the build, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5dcd92399e2d3f304352f2170dd3ef8761e86541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79672 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR())Felix Held
Since we have chipset devicetrees for both SoCs supported by the Stoneyridge code, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/amd/picasso/fsp_s_params: use is_dev_enabledFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b692aaa2e3f768cc03bca71eff3ceb1a8733ad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79670 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26soc/intel/alderlake: Make C1e configurableSean Rhodes
Make it possible to enable C1e from the devicetree by adding `c1e_enable`. C1e was disabled by ea2a38be323173075db3b13729a4006ea1fef72d for all RPL SOCs to reduce noise. This will ensure that boards that disabled it based on CPUID are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I758621393cb39345c2ba7b19a32872e84e1c5a19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77088 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26sb/intel/bd82x6x/pch: Add method to identify PCHPatrick Rudolph
Identify PCH type by LPC device ID. This allows to identify the PCH without including northbridge headers. Tested: Lenovo X220 still boots. Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-26mb/google/zork/dsdt: move LIDS object right after dsdt_top.aslFelix Held
This is a preparation to make the next patch result in identical images for timeless builds and also aligns Zork's DSDT more with Guybrush's DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-26soc/intel/xeon/spr: Enforce POR frequency settingNaresh Solanki
For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-23sb/intel/bd82x6x: Add defines for PCI IDsPatrick Rudolph
Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23nb/intel/{gm45,sandybridge}: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-23mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460pRiku Viitanen
Extracted from a system running OEM BIOS version F.42. intelvbttool --inlegacy --outvbt data.vbt Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79625 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23.gitreview: Update default branch from master to mainArthur Heymans
The master is deprecated in favor of the main. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I58001819079bc880e8cde1c3a6756ff6c8a1c016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-23sb/intel/bd82x6x: Honor POST code Kconfig optionKeith Hui
This southbridge can route POST codes written to port 0x80 to either LPC or PCI, but currently always route them to LPC. Change it so that POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is selected, LPC otherwise. Rename the static function because POST codes no longer always go to LPC. Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-23mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,the values before Sensor1 and Sensor2 were set too high. Modify the protection temperature to better meet DUT requirements. BUG=b:291217859 BRANCH=none TEST=emerge-rex coreboot Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik
This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22drivers/intel/fsp2_0: Log FW Splash Screen feature stateSubrata Banik
This patch implements debug logging to aid debugging and analysis of Firmware Splash Screen feature behavior. BUG=b:284799726 BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/screebo and check the FW splash screen state. [DEBUG] Firmware Splash Screen : Enabled Change-Id: I1ec7badf620e8dbe3d48674d93d640161de6a830 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22soc/intel/cmn/block/pmc: Add previous sleep state strings in logMarx Wang
Previous sleep state showing in serial log is a magic number. In order to let users understand its meanings directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [DEBUG] prev_sleep_state 0 with this change: [DEBUG] prev_sleep_state 0 (S0) Change-Id: Iabe63610d3416b3b6e823746e3ccc5116fabb17d Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-22mb/google/rex/var/karis: Adjust touchscreen power-on sequenceTyler Wang
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high should over 5ms. And current measure result is 200us. Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet requirment. Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high: Power on --> 31.7 ms Resume --> 38.7 ms BUG=b:314245238 TEST=Measure the sequence Change-Id: I56e455a980b465f27794b30df058ec0944befc2e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42Jeremy Compostella
Meteor Lake CPUs physical address size is 46 if TME is disabled, 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79666 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22x86: Separate CPU and SoC physical address sizeJeremy Compostella
The physical address size of the System-on-Chip (SoC) can be different from the CPU physical address size. These two different physical address sizes should be used for settings of their respective field. For instance, the physical address size related to the CPU should be used for MTRR programming while the physical address size of the SoC should be used for MMIO resource allocation. Typically, on Meteor Lake, the CPUs physical address size is 46 if TME is disabled and 42 if TME is enabled but Meteor Lake SoC physical address size is always 42. As a result, MTRRs should reflect the TME status while coreboot MMIO resource allocator should always use 42 bits. This commit introduces `SOC_PHYSICAL_ADDRESS_WIDTH' Kconfig to set the physical address size of the SoC for those SoCs. BUG=b:314886709 TEST=MTRR are aligned between coreboot and FSP Change-Id: Icb76242718581357e5c62c2465690cf489cb1375 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79665 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22Revert "cpu/intel/common: Define build time physical address reserved bits"Jeremy Compostella
This reverts commit 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-22Revert "soc/intel/meteorlake: Set build time physical address reserved bits"Jeremy Compostella
This reverts commit 533efb23083afd721d4c268ce0ee8e863e13689a. BUG=b:314886709 Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79664 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22mb/google/nissa/var/gothrax: Add probe for Type-C Port C1 (DB)Yunlong Jia
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board). DB_A is only used for skus without Type-C Port C1. BUG=b:316048649 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ifb702c497740953144b43c56653da16fade1053f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629 Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22mb/google/brox: Fix config errors with 8 GPIOsShelley Chen
Some GPIOs were not configured correctly according to the HW spreadsheet provided by the HW team. * GPP_B5/GPP_B6 use NF1, not NF2 * GPP_B23 should use NF2, no GPI * GPP_D11 should be set to NC * GPP_E21/22 should be using NF (previous NC) * GPP_F17 is a GPO * GPP_F18 should be an interrupt, not a NF BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-22mb/google/brox: Align GPIO reset with HW spreadsheetShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL are to fix the pad's reset field as needed. See "Intel SoCs" section in https://doc.coreboot.org/getting_started/gpio.html for reset definitions. BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-22mb/google/brox: Fix pulls as necessaryShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL include fixing the pulls for GPIOs as necessary, making sure that it matches what is in the HW team's spreadsheet. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22mb/google/brox: Change unused GPIOs to NCShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes here include changing the pad config to NC because it is not being used in ChromeOS. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-21drivers/spi/gigadevice.c: Add GD25LQ255E supportTyler Wang
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf BUG=b:311336475 BRANCH=firmware-rex-15709.B TEST=Build AP-firmware and test on karis, system can boot to OS. Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-21mb/google/rex/var/karis: Add HDMI/eDP GPIOs to early GPIO listTyler Wang
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:316982707 TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Remove Camera EEPROM off timingWentao Qin
Since the camera sensor and camera eeprom share GPP_A12, remove the off timing to avoid issue of camera sensor loss, but this will increase system power by 5mW. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:298126852 TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost. 2. Run S0ix check to see if the camera function abnormal. Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647 Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Configure slew rate to 1/8 for GT domainKun Liu
set slew rate to 1/8 for GT domain. BUG=b:312405633 BRANCH=none TEST=Able to build and boot google/screebo Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-12-21mb/google/{brya,brox,rex}: Update ec_sync wake capabilityMark Hasemeyer
Some of the boards use the EC_SYNC pin to wake the AP but do not advertise the pin as wake capable in the CREC _CRS resource. Relevant boards were determined through empirical testing and inspection of gpio configuration. Update the ACPI tables for rex, brya, and brox based boards to advertise their EC_SYNC pin as wake capable. BUG=b:243700486 TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined -Wake Aviko via keypress and verify chromeos-ec as wake source -Wake Screebo via lid open and verify chromeos-ec as wake source Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20.editorconfig: Add indent style & size of 2 spaces for shellMartin Roth
This adds a default style for shell scripts. fmtsh now looks for this when reformatting shell scripts. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I348f23badf302a48c851231a08c1ce4be94738a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20mb/amd/onyx_poc/devicetree: enable UART0Felix Held
UART0 is routed to a USB-serial converter chip on the Onyx board, so also enable this UART in the devicetree, so that the OS will be able to use this UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-20mb/google/brox: Enable FSP UPD LpDdrDqDqsReTrainingIvy Jian
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:311450057 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20device/i2c_bus.c: Check pointer for NULL before using itMartin Roth
Found-by: Coverity Scan #1489753 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f3794cf17875cdb35010c79a6537a4c13a18224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-20nb,sb/amd/pi/*/pci_devs: drop unused PCI device IDsFelix Held
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even though they're unused at the moment, but those might still be useful to keep around, since the SATA controller can have different PCI device IDs depending on in which mode it is in. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20mb/google/rex/variants/deku: correct GPIO configurationEran Mitrani
GPP_B02 and GPP_B03 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/google/rex/var/karis: Add PANEL_PWRSEQ_EC_CONTROL in fw_configTyler Wang
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL". Add this field in coreboot for align fw_config settings. BUG=b:314245238 TEST=emerge coreboot pass Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20mb/google/rex/var/karis: Update fw_config FAN fieldTyler Wang
After confirm with thermal, only EC will reference FAN field in fw_config. Update the settings for align fw_config. BUG=b:307822225 TEST=emerge coreboot pass Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-12-20soc/amd/genoa_poc: select DEFAULT_X2APICVarshit Pandya
Allow SoC code to set LAPIC access mode to X2APIC Change-Id: I208cca35c328e1566a57aaaa8ee7809e0760261c Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20mb/amd/onyx_poc/devicetree: Enable UART1Varshit Pandya
UART1 is selected for debug uart in Kconfig, it also needs to enabled in devicetree. With this serial output doesn't stop during the device enable step. TEST:Build onyx_poc board Change-Id: I7c910301c6eca5d3057785607139ac03b344bc15 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20util/{cbfstool,nvramtool}: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I2dd0c2ccc4f4ae7af7dd815723adf757244d2005 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20mainboard: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20arch/riscv: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: Icf41e823c42ffea7b73bdd9112081af4d1f94bc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20commonlib/bsd: Tag CBMEM IDs deprecated for crashlogPratikkumar Prajapati
These IDs are not used as crashlog data is not stored in CBMEM now. (Ref CL: I43bb61485b77d786647900ca284b7f492f412aee Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog) BUG=b:298234592 TEST=Able to build REX. Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20soc/intel/common,mtl: Refactor BERT generation flow for crashlogPratikkumar Prajapati
With earlier flow, a chunk of CBMEM region was allocated for each SRAM e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM content was copied to dedicated CBMEM region. Later in acpi_bert.c, the BERT table was getting created for each chunk of CBMEM. This flow was not considering creating separate entries for each region of crashlog records. It resulted in only the first entry getting decoded from each SRAM. New flow aims to fix this issue. With new flow, a simple singly linked list is created to store each region of crashlog records from all SRAMs. The crashlog data is not copied to CBMEM. The nodes are allocated dynamically and then copied to ACPI BERT table and then freed. This flow also makes the overall crashlog code much simpler. BUG=b:298234592 TEST=With this change decoding crashlog show comprehensive details, tested on REX. Change-Id: I43bb61485b77d786647900ca284b7f492f412aee Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20acpi: Reduce wait interval in delay loop for sleepSukumar Ghorai
The optimization of sleep time in acpi code includes reducing the sleep duration and increasing the polling frequency within the acpi _ON/_OFF method. StorageD3Enable is activated in Google/Rex, and this optimization results in a saving of approximately 25ms in D3cold resume time, reducing it from around 160ms to 135ms. BUG=b:296206467 BRANCH=firmware-rex-15709.B TEST=boot test verified on google/rex verified _ON/_OFF Method in SSDT. verifid kernel log in s0ix test - 0000:00:06.0: PM: pci_pm_resume_noirq Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-12-20mb/google/rex/var/screebo: Configure Acoustic noise mitigationSubrata Banik
Enable Acoustic noise mitigation for google/screebo and set slew rate to 1/8 for IA domain and ignore the slew rate for SA domain. BUG=b:312405633, TEST=Able to build and boot google/screebo. Before: [SPEW ] AcousticNoiseMitigation : 0x0 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x0 [SPEW ] SlowSlewRate for Index = 0 : 0x0 After: [SPEW ] AcousticNoiseMitigation : 0x1 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x1 [SPEW ] SlowSlewRate for Index = 0 : 0x2 Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20soc/intel/meteorlake: Add Acoustic Noise Mitigation UPDsSubrata Banik
This patch allows to override acoustic noise mitigation FSP UPDs: - AcousticNoiseMitigation - FastPkgCRampDisable - SlowSlewRate BUG=b:312405633 TEST=Able to override the acoustic noise UPDs. Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-20vc/intel/fsp/mtl: Add UPDs for Acoustic Noise MitigationSubrata Banik
Acoustic noise in PCBs is a common problem and be caused by a variety of factors, including: Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal expansion. This patch adds the UPDs to FSPM header file for mitigating the acoustic noise. FSPM: 1. AcousticNoiseMitigation 2. FastPkgCRampDisable 3. SlowSlewRate BUG=b:312405633 TEST=Able to build and boot google/rex. Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20clang-format: Update configuration for version 16+Martin Roth
As we look at unifying the format of coreboot code (/src, excluding src/vendorcode), we need a code-beautifier configuration that works well with the coreboot style. This patch is an attempt to match the existing code styles as much as possible. There are going to be some trade-offs in any code formatter. Tables which have been hand-formatted probably won't look as good. These can be specifically marked to be excluded from the formatter, however this should be the exception, not the rule. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I70341d77e167c145f447594b6b0bef628cea83c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78832 Reviewed-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19sb/intel/bd82x6x/pch.c: Extract common functionsAngel Pons
PCH identification functions and `pch_iobp_update` are used in multiple stages. Move them out of `pch.c` to drop some ugly preprocessor usage. Subsequent commits will use `pch_iobp_update` in romstage as well. Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624 Reviewed-by: Naresh <naresh.solanki.2011@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19mb/google/rex/var/screebo: Add delay 1ms after Main 3V3Kun Liu
when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDDWeimin Wu
For EVT SCH: 1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera. 2. Delay reset for 5ms when device power on. BUG=b:312663347 TEST=1. Google Camera app working 2. Passed EA verified Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-19device: Drop MULTIPLE_VGA_ADAPTERS KconfigNico Huber
This option is nowhere selected and there is only a single case left where it's used. Guarding the check in pci_rom_load() seems like a bad idea: As the code would be copying all VGA ROMs to the same location, it would be only working by chance (if the last encoun- tered ROM is the right one). Hence, drop the guard and always check for the correct device. Change-Id: Ib283bf0a65367b99099a3bfcbd27585d44235eb9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79596 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19nb/amd/pi: drop HW_MEM_HOLE_SIZEK Kconfig optionFelix Held
There's neither need to remove get_hw_mem_hole_info from the code if the Kconfig option was set to 0 nor the actual value didn't make any difference in the behavior of the code: When node_id has still its initial value of -1, domain_read_resources won't use the value of hole_startk, and when node_id is set to 0, get_hw_mem_hole_info also sets hole_startk to the actual value that then gets used by domain_read_resources. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieffab695a3151ed7f6bf9d6c880bbb43eecf7893 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79609 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19nb/amd/pi/00730F01/northbridge: use devicetree device pointersFelix Held
This APU is always a single-node, so the nodeid parameter of get_node_pci is always 0. Since this SoC has a chipset devicetree, we can just use DEV_PTR(ht_X) instead of the pcidev_on_root call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bf9d214b4c2e5d995976fb79fef6fe43a6e9fa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79608 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19nb/amd/pi/00730F01/northbridge: assume that there's DRAMFelix Held
This APU is always a single-node and since we're in ramstage when domain_read_resources gets called, there's DRAM on this node, so no need to check for this. To be extra sure, also initialize basek and limitk before calling get_dram_base_limit with pointers to those as arguments. This won't be necessary for the code to work as intended, but will probably keep the compiler from complaining. Also move the declaration of basek, limitk and sizek to the beginning of the function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ef8011eb57b16218b8f5fea295900b855c3014b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79611 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19nb/amd/pi/00730F01/northbridge: rework idx in domain_read_resourcesFelix Held
Start with the resource index 0 and increment it after reporting each resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fb59ff3d371b744b53093d17392d1c3510bef82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 12:31:52 +0000