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On Broadwell, this reduces the number of 'remarks' in the IASL build
from 222 to 3.
Fixes these remarks:
Object is not referenced (Name is within method [_CRS])
The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method. Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.
This change was made for fsp_baytrail in commit 2eaa0d49
fsp_baytrail: Fix ACPI 'Object is not referenced' warnings
Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11882
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.
Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/cpu/intel/model_6dx/acpi`, although the devices
can also use different Intel CPU models like, for example,
`intel/model_6ex` on the Lenovo T60.
Therefore move the file to the directory `src/cpu/intel/common/acpi` so
that other devices, like Intel GM45 based devices, can also include it.
Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
configuration option.
TEST=Built and booted on Minnowboard Max
Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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connections checked by desoldering the FCH and looking at the PCB
this lowers the power consumption by about 150-200mW measured on primary side
based on change #5397
Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/11866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch fixes compilation of cbfstool on Cygwin.
As reported in http://review.coreboot.org/#/c/10027
cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE.
That patch was abandoned because it would unwantedly turn on
more GNU extensions. Instead of doing that, only enable the
define on Cygwin, switch to -std=gnu99 instead of -std=c99 to
make fileno and strdup actually available.
A MINGW32 check that was forgotten in Makefile was copied over
from Makefile.inc to keep the two files in sync.
This patch has no impact on non-Windows builds.
Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11667
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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don't use non-volatile pointers for MMIO access
Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12081
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11950
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I3623f8945bd62b7050ec609934f96543552c792b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12018
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11990
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
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Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11945
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
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Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11948
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11942
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
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Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11955
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
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The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.
Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.
Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This utility should make it easier to complete and maintain
the database of coreboot subsystem maintainers (MAINTAINERS
file)
This will need a bit of tender love and care to print information
in an easily machine readable output for the build system, but its
a first start to query the maintainers database.
Build with:
$ go build util/scripts/maintainers.go
Find a maintainer for a set of files with:
$ ./maintainers Makefile Makefile.inc
Makefile is in subsystem BUILD SYSTEM
Maintainers: [Patrick Georgi <patrick@georgi-clan.de>]
Makefile.inc is in subsystem BUILD SYSTEM
Maintainers: [Patrick Georgi <patrick@georgi-clan.de>]
Check the maintainer database with:
$ ./maintainers
.gitignore has no subsystem defined in MAINTAINERS
.gitmodules has no subsystem defined in MAINTAINERS
.gitreview has no subsystem defined in MAINTAINERS
3rdparty/arm-trusted-firmware has no subsystem defined in MAINTAINERS
3rdparty/blobs has no subsystem defined in MAINTAINERS
3rdparty/vboot has no subsystem defined in MAINTAINERS
COPYING has no subsystem defined in MAINTAINERS
Documentation/AMD-S3.txt has no subsystem defined in MAINTAINERS
Documentation/CorebootBuildingGuide.tex has no subsystem defined in MAINTAINERS
Documentation/Doxyfile.coreboot has no subsystem defined in MAINTAINERS
[..]
Change-Id: I49c43911971152b0e4d626ccdeb33c088e362695
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11944
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
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Cygwin complains:
cbfstool.c: 1075:5 error: array subscript has type 'char' [-Werror=char-subscripts]
so add an explicit cast.
Change-Id: Ie89153518d6af2bacce3f48fc7952fee17a688dd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11666
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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To help hypervisors to assign PCI devices individually to virtualization
guests, page align dynamically allocated MMIO resources.
Tested with kontron/ktqm77 which has dynamically configured onboard
devices on the root bus and secondary buses. Booted Linux and checked
the configuration with `lspci -v`. Got the configuration through Muen's
tools which are very picky about overlapping and alignment. Booted a
Muen based system that uses many onboard devices. GMA, xHCI and one NIC
(on a secondary bus) were verified to function properly.
Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12111
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I783aa4b2319aaedd57ce9a67ca935392a611298f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Id8dda8a973dcf991ac494c2d50258d1b51e43c6a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Values based on correlation of brand strings, brand numbers and the TDP
listings on AMD's web site (Wikipedia for Athlon 64 FX-7x TDPs).
Change-Id: I7e6d12d0b6cc4fefc3f84076234c62c40e08304c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10926
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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According to the documentation further up in the file:
F: drivers/net/ all files in and below drivers/net
F: drivers/net/* all files in drivers/net, but not below
F: */net/* all files in "any top level directory"/net
Add trailing slashes to directory names.
Change-Id: I7bfd2eb2528a75fb6af79a990acb89f5e4251383
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12118
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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vboot2 in payloads (eg depthcharge) needs it.
Change-Id: I4e79ae29cc282c8680f21686befd35c4ff461b3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It works there, we want it, disable that restriction.
Change-Id: Idc023775f0750c980c989bff10486550e4ad1374
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/12094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This reverts commit e6606518243d9beda31693d40493b5f7a1a3e2e0.
After some discussion on IRC we decided to revert it as libpayload can
only read the copy that was removed (and other users like nvramtool can
only read the other copy). So we need both copies at this time.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
Reviewed-on: http://review.coreboot.org/11696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iaee7e2c74fe9f63d4d4878278bd445af393942f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11920
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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We need to special-case filling out the vboot structures when
we use CBFS instead of vboot's custom indexed format, otherwise
(due to the way the CBFS header looks), it will try to write several
million entries.
Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This way, commit differences will be easier to read. Also sort the list
lexicographically.
Change-Id: I4ce3ac9018a3fddf5e30d7c1ac0c57090fac1d3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12084
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Currently, cbfstool regressed that removing a file from CBFS the space
is marked as empty but the filename is still shown, preventing adding a
file with the same name again. [1]
```
$ echo a > a
$ echo b > b
$ ./util/cbfstool/cbfstool test.rom create -m x86 -s 1024
Created CBFS (capacity = 920 bytes)
$ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw
$ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw
$ cp test.rom test.rom.original
$ ./util/cbfstool/cbfstool test.rom remove -n
$ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom)
--- /dev/fd/63 2015-08-07 08:43:42.118430961 -0500
+++ /dev/fd/62 2015-08-07 08:43:42.114430961 -0500
@@ -1,4 +1,4 @@
-00000000 4c 41 52 43 48 49 56 45 00 00 00 02 00 00 00 50 |LARCHIVE.......P|
+00000000 4c 41 52 43 48 49 56 45 00 00 00 02 ff ff ff ff |LARCHIVE........|
00000010 00 00 00 00 00 00 00 28 61 00 00 00 00 00 00 00 |.......(a.......|
00000020 00 00 00 00 00 00 00 00 61 0a ff ff ff ff ff ff |........a.......|
00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
$ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw
$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86
Name Offset Type Size
c 0x0 raw 2
b 0x40 raw 2
(empty) 0x80 null 792
```
So it is “deteled” as the type changed. But the name was not changed to
match the *(empty)* heuristic.
So also adapt the name when removing a file by writing a null byte to
the beginning of the name, so that the heuristic works. (Though remove
doesn't really clear contents.)
```
$ ./util/cbfstool/cbfstool test.rom remove -n c
$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86
Name Offset Type Size
(empty) 0x0 null 2
b 0x40 raw 2
(empty) 0x80 null 792
```
[1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html
Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11632
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Change-Id: Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Behave as nvramcui.
Avoid a "General Protection Fault Exception" when launched by SeaBIOS on
pcengines APU1.
Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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TinyCursess is officially spelled in CamelCase [1].
[1] https://github.com/tommyettinger/TinyCurses
Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11727
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11726
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Instead of adding code to generate the junit.xml file for jenkins to
each of the util makefiles, add it once to the top level Makefile.inc.
Create a list of tools to run the test on.
Add nvramtool and inteltool to the list of utilities tested.
Note that the util builds depend on implicit rules, so MFLAGS and
MAKEFLAGS have to be cleared to get the builds to work.
Change-Id: Id7ee5ea41ce3bf4a40fb50942ae785bb838fa639
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.
Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This will run the lint-stable scripts on jenkins to block a commit with
obvious and known errors.
It runs in under a second on my system, so shouldn't contribute to any
real delay on jenkins.
Change-Id: I6ff3468ec29dc4ccd0c115f2c26e26b291c507df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11892
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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When the script was pulled out of the makefile, it was left as it was
written in the makefile to show the continuity with the original. This
patch cleans up issues identified by shellcheck and adds comments.
Change-Id: I5e6573a4fdfbb397e15db38e2e3dfadeb3430573
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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To add lint to jenkins testing, we need junit.xml output. This adds an
optional --junit command line parameter to enable output to an xml file
in the lint directory.
Change-Id: I5588190cb050b9dbe99458cb18a71a147769f50e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11891
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In preparation for adding junit xml to the lint tests, move the
script out of Makefile.inc and into its own file.
Add a copyright, usage, and error checking that was not needed
inside the Makefile.
Change-Id: I32bebc6a5f1f6fa652812c8a014d84006e2e6c8a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11890
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Merge artifact -- don't check spd_index twice.
BUG=None
TEST=Build only
BRANCH=Auron
Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234421
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
(cherry picked from commit 850125141b52886c845161434a1320676e59534d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05
Reviewed-on: http://review.coreboot.org/11912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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These are needed for the hardware-sequencing function of the PCH SPI
interface. Values are specific to the flash chip used on a board.
Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11798
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.
In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().
BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron
Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
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Do not hardcode the CPU downstream non-posted request limit; the
value of this register is CPU family specific and is set appropriately
in the corresponding CPU driver code.
Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11935
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Change-Id: I975142351c0c033f9dc44670dcf819d296896921
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11934
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I6a32b69d3b75d7d086dc7f8ea1e195473399f406
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11933
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: Icd28af388c49ad36d7a8e414b3c82e18e1f8f523
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11932
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Commit dbeedbef (arch/x86/bootblock: Link in object files selected with
bootblock-y) breaks building of x86 boards with
`CONFIG_EARLY_CBMEM_INIT` *not* selected but CBMEM time stamp collection
enabled.
Aaron Durbin explained as below [1] and provided this patch to fix it.
> That change actually processes bootblock-objs where before it never did
> such a thing. I'm sure this isn’t the only issue lurking. bootblock on
> x86 implied romcc and thus all the bootblock-y += rules that other
> architectures use worked, but now all the implied assumptions are no
> longer true on x86.
>
> timestamp stuff on x86 !CONFIG_EARLY_CBMEM_INIT is the issue you're
> seeing. In order to compile timestamp.c for bootblock under these
> conditions will mean there needs to be some more Makefile guarding.
[1] http://review.coreboot.org/11864
Change-Id: I3441b9fcdbbc8bbe82b9f2075e60668a846ecf09
Fix-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I626a11c17c9d05c174c507d50684e498c8604cbc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The broadwell soc code was upstreamed based off an old coreboot branch
and apparently never tested with USBDEBUG.
This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
board, as verified with a FT232H setup. The fix is simply removing
outdated code that since branching off had been deduplicated in upstream
coreboot, anyway.
Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: http://review.coreboot.org/11874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Instead of renaming the junit filename, send abuild the desired
name on the command line.
Change-Id: I779bc180343bd549908750d7128bedbab7f36266
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The 'what-jenkins-does' makefile target was renaming the junit filename
after abuild finished. Instead, just add a command line parameter to
send it to a different filename.
Change-Id: I66f7d80d621573d77a5154f36f2db49d7b2e948a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Serial number is derived from the MAC address of first NIC.
Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Do this to wipe error message and hexdump of SPD from console log.
Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.
Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ia158b4c6c12fb6e22ea7fed9035574a3abedf98c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11885
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The existing microcode update system used custom, manually generated microcode
blob files. This made updates very difficult. Update parser to use stock
microcode update files as provided by AMD.
Change-Id: I772b264ad167f2a5d629dab5d64d9b0ccab3a053
Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11829
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.
- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning. To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings
Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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In order to support verstage the cache-as-ram split
is taken advantage of such that verstage has the
cache-as-ram setup and rosmtage has the cache-as-ram
tear down path. The verstage proper just initializes
the console and attempts to run romstage which triggers
the vboot verification of the firmware. In order to
pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning
to the assembly code which tears down cache-as-ram.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with verstage support as well as
VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.
Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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To support x86 verstage one needs a working buffer for
vboot. That buffer resides in the cache-as-ram region
which persists across verstage and romstage. The current
assumption is that verstage brings cache-as-ram up
and romstage tears cache-as-ram down. The timestamp,
cbmem console, and the vboot work buffer are persistent
through in both romstage and verstage. The vboot
work buffer as well as the cbmem console are permanently
destroyed once cache-as-ram is torn down. The timestamp
region is migrated. When verstage is enabled the assumption
is that _start is the romstage entry point. It's currently
expected that the chipset provides the entry point to
romstage when verstage is employed. Also, the car_var_*()
APIs use direct access when in verstage since its expected
verstage does not tear down cache-as-ram. Lastly, supporting
files were added to verstage-y such that an x86 verstage
will build and link.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using separate verstage.
Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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When a separate verstage is employed the verstage file
was just being added through the cbfs-files mechanism.
However, that doesn't allow one to specify other flags
that aren't supported that an architecture may require.
The x86 architecture is one of those entities in that
it needs its verstage to be XIP. To that end provide
a mechanism for adding verstage with options.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using his mechansim on x86.
Change-Id: Iaba053a55a4d84d8455026e7d6fa548744edaa28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11819
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
internal USB EHCI controller broken, with no assigned IRQ.
PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
for the GPIO to use. They cannot be used for PCI devices at the same time.
Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9993
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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If timestamps need to be enabled for t132-boards, build would break
because TIMESTAMP region does not exist. With this change, t132 boards
can enable "COLLECT_TIMESTAMPS" without any build error.
Change-Id: I283a5ec49b5af95bd524f590e352367b7cbfd83d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Changes to CR1 and CR2 were effectively overwriting the backlight
configuration from the devicetree with static values.
Instead read the maximum brightness value from BCLM (backlight
modulation frequency) and calculate the target level (Arg0 is the
target level as percentage).
Turned out that _BQC has to return a value from the list returned by
_BCL. So XBQC got a little heavier to search for the correct value.
Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11704
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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The two cases only differ in the register locations.
As the values in BRIG were all the same, consolidate them. They also
got normalized to percentages as the ACPI spec wants that (0x61 was 100%
before).
Change-Id: I9216a953bb89458ed102c39194ea370cbf463d5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11703
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Consolidate some common (and mostly broken) code. Will try to fix things
in separate commits.
Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for
i945 and sch. But this needs further investigation.
Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11702
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
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The right files just need to be added to the verstage
build. Do that so a stand alone verstage builds and
links.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11828
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The current method was only taking the cbfs path. Because
of this fsp.bin was never being utilized from the RW slots.
Using prog_locate() now provides both the cbfs and vboot
locate methods for free.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I2b3e088326d5a965ad90806a7950b9f401ed57de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Leave the SPI controller enabled upon boot block exit.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Move base address into iomap.h. Use PCI symbols instead of SPI specific
symbols. Fix comments.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to support x86 verstage proper the work buffer
needs to live in cache-as-ram. However, after cache-as-ram
is torn down one still needs the verification results to
know which slot was selected. Though the platforms with
a dedicated SRAM can just use the work buffer in SRAM, the
x86 cache-as-ram platforms need a place to stash the
results. For that situation cbmem is employed. This works
because when cbmem is initialized cache-as-ram is still
enabled. The VBOOT_DYNAMIC_WORK_BUFFER case assumes
verified boot doesn't start until after cbmem is up. That
doesn't change, but it's a goal to get rid of that option
entirely once all other x86 platforms are moved over to
pre-romstage vboot.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with pre-romstage verification
as well as VBOOT_DYNAMIC_WORK_BUFFER case.
Change-Id: I7eacd0edb2b6ca52b59b74075d17c00b50676d4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11821
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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On x86 the early stages are currently execute-in-place which
means they live in the memory-mapped spi flash. However, when
loading romstage from verstage the romstage is
execute-in-place so it's unnecessary to write over a read-only
media -- not to mention writing to read-only memory is wrong
to begin with.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Noted reduction of 20ms when
loading romstage.
Change-Id: I7cd399302a3925a05fbce82600b4c50ea66a0fcb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11823
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Bump up the romstage size to allow more breathing room.
Change-Id: I4df7031d286c13797dccdf2f49d023bbf462fbb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11830
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The conditions in cbmem console for supporting verstage
were implicitly utilizing CONFIG_BOOTBLOCK_CONSOLE to handle
the cbmem console enablement. Fix it so verstage is a first
class citizen for deciding actions pertaining to cbmem console.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using verstage. cbmem console
shows verstage output.
Change-Id: Iba79efd1c1d4056f1a105a5e10ffc95f3e69b597
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11820
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For the purpose of isolating the work buffer logic
the surface area of the API was slimmed down. The
vb2_working_data structure is no longer exposed,
and the function signatures are updated accordingly.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: If64184a79e9571ee8ef9822cfce1eda20fceee00
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11818
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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For vboot1 there was an rmodule that was loaded and ran to
do the firmware verification. That's no longer used so remove
the last vestiges of VBOOT_STUB.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I6b41544874bef4d84d0f548640114285cad3474e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11817
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The report_platform_info() and set_max_freq() are not being
used similarly on skylake and braswell. With the addition
of other SoCs I suspect a similar pattern will emerge. Instead
of having weak functions to ensure things link with the hardcoded
policy push these calls into their respective SoC homes.
For parity, both skylake and braswell were updated to be consistent
with the same calls prior to this patch.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Built braswell.
Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303334
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11815
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Eliminate unused parameters from the console initialization.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301204
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Latest FSPv83 made some change related to UPD/VPD
need this patch to align those
BUG=None
TEST=Build and Boot Cyan System
BRANCH=strago-7287.B
CQ-DEPEND=CL:*226897
Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291394
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303137
Original-Commit-Ready: John Zhao <john.zhao@intel.com>
Original-Tested-by: John Zhao <john.zhao@intel.com>
Change-Id: I9920eea84b802699454850bfde489668201ffeb6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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On Skylake, mailbox interface is used to configure VRs, dropping direct msr
writing. With current fsp, svid/vr programming seems to be functional - no
errors are given in the svid transactions in boot, and hw engineer verified
the VRs on Kunimitsu. Additional tunnings might be needed later with power
testing.
24mhz calibration is no longer needed on Skylake due to bclk archtecture
change.
BRANCH=none
BUG=chrome-os-partner:45387
TEST=Built and boot on kunimitsu/glados, reboot, S3/resume verified.
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Change-Id: If99b5758fcdba8604139c761a07403d4a5d2eb4c
Original-Reviewed-on: https://chromium-review.googlesource.com/301470
Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I98acf78aac9c705614fb200f8c3313a89296fbf2
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11811
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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FSP is actually providing 64KiB to the bootloader.
Expand current footprint to match reality.
BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ibff243036eb4a6b9b9f331665a7e3efa1853bc91
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300191
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: Ibb876f49c3e5d8d1a3b8f6f74ed12a19663e4145
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11810
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.
BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It builds only on veyron_* which already select it, no need to ask user.
Change-Id: Ie508b9eade16e0f39073b23dc0da6b6d1e0a4c73
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10380
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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board_id() returns an integer which is platform-specific. 0 for one port
is different from 0 for another port. So there is no default board_id()
and hence enabling it on boards other than urara would cause build failure.
Not enabling it on urara or just setting id to "(none)" as is default results
in board_id() = 0 which means urara and an error message on console.
Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10379
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Fixes linking error. Specifies that we're in text mode.
Change-Id: I7ad258961039c19e1491e2b3832b003671d8a5c7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11848
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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E.g. on my MacbookAir to generate spd.bin to be used
with coreboot I do:
./inteltool -S spd.bin
Change-Id: If165475ed3e1f3262a8926ef619128d25b1e2896
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11847
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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MBa doesn't have a usable usbdebug port.
Change-Id: Ia8459daa5c9b9405c289954b28ecf1423b1f076c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Update to commit 832bc6f1 (Remove microcode stored in C-array format),
which is the latest commit in the BLOBs repository.
Building the Lenovo X60 currently fails as the microcode file cannot be
found.
CREATE build/mainboard/lenovo/x60/cbfs-file.wkWhPK.out (from src/mainboard/lenovo/x60/cmos.default)
make: *** No rule to make target '3rdparty/blobs/cpu/intel/model_69x/microcode.bin', needed by 'build/cpu_microcode_blob.bin'. Schluss.
Change-Id: I40ebceec299f46c19fd60861d872adcd91df3610
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
