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2022-06-10mb/google/brask/variants/moli: correct ddi_ports_configRaihow Shi
1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let tcp0 and tcp2 can display 2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to enable DDC BUG=b:234521799 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/google/brask/variants/moli: enable USB retimerRaihow Shi
Enable USB retimer in moli overridetree. BUG=b:233869074 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVPCliff Huang
In Adl-P RVP, those interfaces are used as USB ports. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVPCliff Huang
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-10ec/google/chromeec: Add support to report fan speed via ACPISumeet Pawnikar
Add fan speed rpm control for DPTF based Active2 policy as per document #626708, by utilizing existing FAN0 variable from src/ec/google/chromeec/acpi/emem.asl#18. There is no corresponding EC change required for this policy support because EC fan code already exporting this rpm value using EC_MEMMAP_FAN for FAN0. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system and verify the fan speed in rpm under sysfs path cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm. Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09soc/amd/sabrina/acpi: Correct VID decoding on SabrinaFred Reitberger
Sabrina uses the SVI3 spec for VID tables which is incompatible with the SVI2 spec used on PCO/CZN. Move the defines from common to soc and update the decoding for sabrina. See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables TEST=timeless builds on mandolin/majolica for PCO/CZN build chausie and verify pstate power is correct in ACPI tables Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I915e962f11615246690c6be1bee3533336a808f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-09payloads/tianocore: Allow custom build parametersMichał Żygowski
Currently, custom TianoCore builds are allowed, but those may need different parameters. Add a Kconfig option to specify additional parameters to be appended to build command. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I025459ae94592103b4be0c68b422100b7c649d34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/google/dedede/var/shotzo: Deselect BASEBOARD_DEDEDE_LAPTOPTony Huang
Shotzo is not a laptop (it is a Chromebase), therefore deselect BASEBOARD_DEDEDE_LAPTOP. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/dedede: Create shotzo variantTony Huang
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-06-09mb/google/brask/variants/moli: remove mainboard_vbt_filename in ramstageRaihow Shi
mainboard_vbt_filename() is to decide which VBT to return, but moli only has one VBT, so it doesn't need this function. BUG=b:234521809 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/alderlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
This patch provides an option for CPU programming where coreboot expected to load second microcode patch after BIOS Done bit is set and before setting the BIOS Reset CPL bit. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor LakeSrinidhi N Kaushik
Add header files generated from FSP 2173_00 source build for Meteor Lake platform. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-09soc/intel/alderlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. This patch is the Alder Lake equivalent of CB:59024. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-09soc/intel/apollolake: Correct the maximum number of Heci devicesSean Rhodes
Both APL and GLK have 3 Heci devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-09soc/intel/alderlake: add support for external source clockCliff Huang
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9. This allows boards to use source clock 7, 8, 9. BUG=b:233252409 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09soc/intel/alderlake: Add support for PCIe slot & device detect timeoutCliff Huang
1. add timeout for root port detection and pass to FSP. 2. add 'slot implemented' flag and pass to FSP. 3. PcieRpSlotImplemented needs to be set when the root port is set to hotplug. There is an assertion in FSP checking this. 4. PcieRpSlotImplemented is updated only when it is built-in as it is default to slot implemented in FSP. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-09mb/google/brya: Create ghost4adl variantJack Rosenthal
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-09mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portIvy Jian
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`. The change is required to detect USB2 device on type-C port of Agah boards. BUG=b:233554817 TEST=build and test USB2 hub could be detected on both the Type-C ports. ================================================================= usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00 usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 3-3: Product: USB 2.0 Hub hub 3-3:1.0: USB hub found hub 3-3:1.0: 4 ports detected ================================================================= Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang
Add craaskbowl supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP 2. Hynix H9JCNNNCP3MLYR-N6E BUG=b:235134420 TEST=Use part_id_gen to generate related settings Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/brya: Add memory parts for CrotaTerry Chen
Add a mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) K3LKLKL0EM-MGCN 3 (0011) H58G56AK6BX069 2 (0010) BUG=b:233830713 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/qemu-armv7: Initialize cbmemArthur Heymans
Change-Id: I607205a0d44c71eb26031ced7a8af303efacd6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09libpayload: Add commonlib/bsd/elog and its dependencyHsuan Ting Chen
Add commonlib/bsd/elog dependency in libpayload. This will allow other payloads (e.g. depthcharge) to implement their own eventlog read and write utilities. Also include commonlib/bsd/elog.c source to libc-srcs. This ensure payloads could utilize commonlib elog helper functions. Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Iae3343e66906a8123b3d8de2b67948f286e4ad32 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntaxFelix Singer
Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntaxFelix Singer
Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idfc08803946cc2d4537db4be8d1bc07e48aa6fed Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I63b8b8a086e2c5ede765855b3c803206edf87690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/cyan: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Ib8719143a5a217173b34931e9c0ef02e9895d0a5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: Ib4e81ea95c6fda0e8f8640671db5ce56f3a1b474 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I04f3cc2dbba59d732c9c52a4b90a32481f9da337 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ib34dc8d84815d0885f30b3ea8ceb2fb95a833d50 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ib96cf05f575a2868b2ad0c00fd5486d6e2c5d90a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I86a11ab5d2667661af3491174001001e644083e3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: If83d7fe29d112ba0ed0f72798f2b5436ecf0a6a2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ief1fe60116645d0cdad9e7ac600bc1062b54b40d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/smsc/mec1308/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ic58e22046aa13549747692f4b21184cf573aa4d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I99cc4cf08ad74f2cb84e0ad16e615e03bbf388af Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, , c)` with `c = a / b`. Change-Id: I9b8262396755197dfbe044e3dc6a6a75c903f093 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I6732fd876524feab924a58434bec381dcdb87bce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/it8518/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Ied407753ee3bb024c8c0350c45312c337ac799e5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/quanta/ene_kb3940q/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Ic04ce82fbfd36bbd2e0cfda1a92ca0a18e1fcd73 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/kontron/it8516e/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I81e976de964f6ae3528884debaf2b24ddf8ed28a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I5c16893b9c98f36fd2c210ed301c2ebb65f95368 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I61ef7b53e851f4c2367cba43ff76b200e9490ad2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: If482b2ad4ba7d4ed1ca8c0695690ede153ed1e2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntaxFelix Singer
Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntaxFelix Singer
Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I24cf4fd70e887c14006975f494be63c34f8a75e6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09sio/winbond/w83627hf/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I9344e34058a1dd8b951d273e53e3c229a0ec07b4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I407d061ac7664d4910b8759fd1a72eab133b6e22 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09superio/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Ia09c54465af47f5779917ed71bb3ea148864dfd1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/google/chromeec/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I2e0c5961fcc90c97666f49837a71f6c0bdc429b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: I256e56841e1c7037fe8ba5e9a963ad2301092325 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ic114e097a08488106554ce2dec61fa219d7cf1d0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I1dbe6c325ed33a4dd15e4d6315b2308d8351974e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09ec/lenovo/h8/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I49a7ed2d57124746815478f3ead8a8f7c54d048a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLessEqual(a, b)` with `a <= b`. Change-Id: Ib00f363b48295ed1c000a839f54d5ea5dc2b88e2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I12c855437a581beade2d218b8f710cf1b32cb841 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Ic9836acb4d32f2ce30c3c6d488bc22ddc64bf365 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09drivers/intel/gma/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Ib1b3f85f95511e903948b385e86e5102d5b43add Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09drivers/intel/gma/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: I56479726f91f33e1d3062a31f1efb82c0814316c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09drivers/intel/gma/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I043ffad90737f4217d01c49e03af81549a0ffb1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I965a0718f6bca1dc27b928bdd9374857f5ea3215 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-08mb/google/brya/var/banshee: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C3 | | C0 C2 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08mb/google/brya/var/brask: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. C2 C0 A3 A2 +----------------+ | REAR | | | | | | | | FRONT | +----------------+ C1 A1 A0 BUG=b:232298007 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08vc/amd/agesa/f15tn: Declare `value` as constant in `GnbRegisterWriteTNDump()`Paul Menzel
Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix the compiler warning below. CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53: src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN': src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 836 | GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value); | ^~~~~ src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE' 68 | #define GNB_DEBUG_CODE(Code) Code | ^~~~ src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'} 86 | IN VOID *Value | ~~~~~~~~~~~~~~~~~~~~~^~~~~ CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level: cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics cc1: all warnings being treated as errors Found-by: gcc (Debian 11.3.0-3) 11.3.0 Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-08mb/google/corsola: Correct EC-is-trusted logicYu-Ping Wu
With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is trusted. However, with Ti50 where corsola has been switched to, it is determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore in the Ti50 case get_ec_is_trusted() can just return 0. The current code of get_ec_is_trusted() only checks the GPIO, which causes the EC to be always considered "trusted". Therefore, correct the return value to 0 for TPM_GOOGLE_TI50. BUG=b:235053870 TEST=emerge-corsola coreboot TEST=firmware-DevMode passed in kingler (with Ti50) BRANCH=none Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08mb/google/brask/var/kuldax: add fw_config and enable BT offloadDavid Wu
add fw_config probe for auido and enable BT offload support. BUG=b:232419816 b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brask/var/kuldax: Update overridetreeDavid Wu
Update override devicetree based on schematics. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brask/var/kuldax: Update gpio tableDavid Wu
Based on latest schematic to update the gpio table. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/redrix: Configure camera EEPROM power always onArec Kao
Remove EEPROM power source interconnect with camera power on/off and keep it always on. There appears to be a rare case where the camera EEPROM is not able to be read from. As a workaround, this patch leaves the EEPROM power rail on in S0. BUG=b:229049914 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-08mb/google/brya: Add GPS _DSM subfunction support for Nvidia GPUTim Wawrzynczak
The _DSM subfunction for the Nvidia GN20 supports 1 additional subfunction, known as GPS, which is required to support GPU Boost. This implementation is minimal, essentially letting the GPU manage its own temperature. BUG=b:214581372 TEST=abuild Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/agah: Fix ACPI power sequencingTim Wawrzynczak
Now that the power sequencing for the GPU is in a better shape, ensure that the ACPI code that performs power sequencing matches the C code that does the same. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/agah: Add delays to GPU power off sequenceTim Wawrzynczak
During the GPU power down sequence, each power rail should reach below at least 10% before the next rail is sequenced down; based on scope shots for a board, conservative delays between each rail are added; they will likely be more fine-tuned later on. BUG=b:233959099 TEST=sequence verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/corsola: Enable ps8640 for steelixZanxi Chen
Currently, the display does not work in steelix. Steelix uses ps8640 eDP bridge IC, which is different from its reference board kingler. So we should enable ps8640 for steelix. BUG=b:232195941 TEST=firmware bootsplash is shown on eDP panel of steelix. Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-08drivers/tpm/cr50: Add TPM IRQ timeout Kconfig optionYu-Ping Wu
The current 10ms timeout for SPI TPM IRQ is not enough for platforms using ti50 (such as corsola). Therefore, introduce a new Kconfig option 'GOOGLE_TPM_IRQ_TIMEOUT_MS'. For platforms using cr50, we need to support legacy pre-ready-IRQ cr50 factory images during the initial boot, so the timeout remains 100ms for I2C TPM and 10ms for SPI TPM. For all the other platforms using ti50, the default timeout is increased to 750ms, as suggested by the ti50 team (apronin@google.com). BUG=b:232327704 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I8dbb919e4a421a99a994913613a33738a49f5956 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-07mb/google/nissa/var/craask: Add MIPI camera settingsTyler Wang
Add OVTI8856 information for craask BUG=b:232656913 TEST=Build and boot on craask Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-07util/util_readme: update to give additional informationMartin Roth
Add a note to the top of the util.md document saying not to edit it. The Documentation/util.md file had been updated to contain additional information at the bottom. This copies that information into the file after it's been created. Change-Id: I4b08439420ceb706df62e3949406585ea34c1514 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07util, Documentation: Run util_readme.sh to regen util.mdMartin Roth
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07cbfstool: Expand CBFS verification validity checkJulius Werner
This patch adds a new line to `cbfstool print -v` output that records the overall CBFS verification health of the image. While this info was already visible from individual fields before, it's nice to have a one-stop location to see "this is a good image" without having to carefully parse a lot of output manually. Also add a few lines to the Makefile that check whether this field is valid for the final image (it always should be, but hopefully this check will allow us to catch regressions like the one fixed by CB:64547 sooner in the future). BUG=b:233263447 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07payloads/external: Reword help of SEAGRUB_ALLOW_SEABIOS_BOOTMENUBill XIE
The sentence about "to bypass the secure mechanism implemented in the GRUB runtime config" sounded confusing, so reword it. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I9c6f40d6d11d459fe4be40a624921c2632a89564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-07Docs: Reword and extend SeaBIOS descriptionBill XIE
The sentence about using SeaBIOS as secondary payload sounded confusing, so reword it. While at it, improve and extend on SeaBIOS features. Change-Id: Ic06b9f56ab8082f2e6eff5fd8d31525429fd948d Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-07mb/google/brya/var/vell: Add new LP5 RAM IDShon
Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign Vendor H58G56AK6BX069 2 (0010) Hynix BUG=b:227595062 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07arch/x86: Add a common romstage entryArthur Heymans
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki
With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07cpu/intel/microcode: Have provision to re-load microcode patchSubrata Banik
This patch provides an option to reload the microcode patch a.k.a second microcode patch if SoC selects the required RELOAD_MICROCODE_PATCH config. There is a new feature requirement starting with ADL to re-load the microcode patch as per new Mcheck initialization flow. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Able to re-load microcode patch as below: [INFO ] microcode: Re-load microcode patch [INFO ] microcode: updated to revision 0x41b date=2022-03-08 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a3c29b3c25fccd31280a2a5a8d4fb22a6cf53bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/64833 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-07soc/intel/cmn/mp_init: Create helper function to load microcodeSubrata Banik
This patch creates a helper function named `initialize_microcode()` to load microcode and ease for all function to peform loading microcode using this helper function. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7155fc2da7383629930ce147a90ac582782fa5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07soc/intel/cmn/block/cpu: Set BIOS_DONE on all CPUsSubrata Banik
As per Intel Processor EDS, BIOS_DONE bit needs to be set on all CPUs via MSR. Also, implement a function to perform any SoC recommended CPU programming prior to post CPUs init. At present calling `cpu_soc_bios_done()` for all CPUs from `before_post_cpus_init()`. Note: It is expected that `before_post_cpus_init()` will be extended with other CPU programming recommendations in follow up patches, for example: reload microcode patch etc. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8066cd724c9f15d259aeb23f3aa71a2d224d5340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-07soc/intel/cmn/cse: Implement heci_init() to initialize HECI devicesSubrata Banik
This patch implements heci_init() API that perform initialization of all HECI devices as per MAX_HECI_DEVICES config. BUG=none TEST=Able to build and boot google/taeko with this change. No CSE error observed with `heci_init()` called from romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake siliconBora Guvendik
Board id is same so use cpuid to decide to use ADL or RPL VBT. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>